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Basic Concepts and Test Generation Methods
Published in René David, Random Testing of Digital Circuits, 2020
Figure 3.1a represents a 3-input, 1-output combinational circuit. Let us denote z0 the output function of the fault-free circuit. Then Z0 = x1 + x2x3. Let f denote the stuck-at fault w/0 and zι the corresponding output function. Then zι = x1.Figure 3.1b presents the truth tables of both z0 and zf Note that they are different for the input vector x1x2x3 = 011, since the output should be 1 and is actually 0 for this input vector (the faulty value is presented in bold). This input vector is then a test vector (or detecting pattern) for the fault f.
Testing of Network-on-Chip Architectures
Published in Santanu Kundu, Santanu Chattopadhyay, Network-on-Chip, 2018
Santanu Kundu, Santanu Chattopadhyay
The test sequence for link testing using the MAF model exhibits some important properties that can be utilized in compact and efficient design of test packets: In each test vector, the logic value in the victim line is the complement of that in the aggressor lines. All aggressor lines are assigned the same logic value. This is required to have the maximum aggression effect on the victim.After applying an exhaustive set of test sequences for a victim, the sequence for testing the next line can be obtained easily by shifting or rotating the test patterns in the previous sequence by exactly one bit.Transition from one test vector to another can often be concatenated such that the total number of test vectors needed to test the MAF faults gets reduced. For example, the “Fast-to-fall” needs the test vector 111 followed by 000, whereas the “Fast-to-rise” needs the test vector 000 followed by 111. Thus, the three-vector sequence 111–000–111 can test both the faults, reducing the required number of test vectors from four to three. As shown in Table 8.1, instead of requiring 12 vectors per wire, application of only 8 vectors per wire suffices to check all six MAF faults.
Low-Power Testing for 2D/3D Devices and Systems
Published in Rohit Sharma, Krzysztof Iniewski, Sung Kyu Lim, Design of 3D Integrated Circuits and Systems, 2018
Lin Xijiang, Wen Xiaoqing, Xiang Dong
Figure 9.24 presents the test ordering scheme to reduce peak temperature in 3D ICs. The test ordering scheme is partitioned into multiple phases, where a subset of test vectors is selected in each phase. The selected test vectors produce the least power transition density on the hot spots, while it is not necessary to produce the least power transition density on all other nodes. Our method does not provide a globally optimal solution for the problem, but a greedy procedure. Power consumption at the combinational part of the circuit is also included by using a cycle-accurate logic simulator. That is, each vector is selected to produce the least power transition density at the hot spots. The second vector is selected under the test responses of the first selected test vector. This process continues until the given number of test vectors has been selected. The thermal information of the circuit is updated after each subset of test vectors has been applied. It is not good to select too many vectors in each phase, which cannot provide accurate enough results for the thermal-driven test application scheme. The number of test vectors chosen in each phase also cannot be very small; otherwise, the CPU time to order tests and the CPU time to complete thermal analysis can be unacceptable. The process continues until all test vectors have been ordered. Actually, the ATE just has a single test phase with the ordered test vectors.
Test Pattern Generator for MV-Based QCA Combinational Circuit Targeting MMC Fault Models
Published in IETE Journal of Research, 2022
The ATPG-generated test vectors are compacted using the Hamming distance-based compaction method. The heuristic used here is to select the test vectors based on total number of don't care bits in the vector. The test vector with minimum don't care bit is selected first and then the test vector with zero Hamming distance with it will be compacted with it. The number of test vectors required for the corresponding MCNC benchmark circuit is mentioned in column V. Fault coverage is mentioned in the last column of Table 4 which is calculated by equation 6. Here, the fair comparison of experimental results obtained by the proposed basic ATPG with the available literature is not possible as there are many discrepancies between them. The major discrepancy is the number of MV gates required to implement the circuit. The circuits used here are synthesized by QSynthesizer while in the literature, the MALS [26] synthesizer is used.
Multi-frame moving video detection algorithm for IOT based on Gauss Monte Carlo particle filter
Published in International Journal of Computers and Applications, 2020
Song Tao, Zhuang Lei, Jing Chenkai
A 14-day UCSD behavioral test set is selected as the test subject, the first 7 days of sequence video is used as the training set and the last 7 days is the test sequence video. The initial abnormal behavior training video sequence is 40, then the total number of samples is 2000, the number of unlabeled frames in the sample pool is 1152, the total number of samples is 56,234, the abnormal behavior test video sequence is 796, and the total number of samples is 38,926. The detection threshold is set to . Two anomaly detectors are used for performance testing: (1) a single model running on the entire data (comparison algorithm); (2) HMM is used to obtain multiple models of time series with running detectors separately (the proposed algorithm). The energy distribution of the test vector is shown in Figure 2.
A feature selection using improved dragonfly algorithm with support vector machine for breast cancer prediction
Published in Computer Methods in Biomechanics and Biomedical Engineering: Imaging & Visualization, 2023
S. Roselin Mary, R. Murali Prasad, R. Suguna
Support vector machine classification makes use of a radial basis function kernel or Gaussian distribution. Since the external summations are random with respect to the test vector, the classification for a test vector can make use of the outcomes of disconnected external summations.