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Digital Systems
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
Festus Gail Gray, Wayne D. Grover, Josephine C. Chang, Bing J. Sheu, Roland Priemer, Rung Yao, Flavio Lorenzelli
Advances in very large-scale integrated (VLSI) processing technology, particularly CMOS, have resulted in nanometer-scale processes with applications at clock speeds of several gigahertz. For example, at the time of this revision the state of the art is fairly well represented by the Intel Core2 Duo processor chip, which is implemented in 65 nm CMOS, consists of 376 million transistors, and clocks at 2.66 GHz. New design challenges must be mastered to realize systems at an ever-increasing clocking rates and circuit sizes. In particular, clocking-related issues of skew, delay, power dissipation, and switching noise can be design-limiting factors. In large synchronous designs, the clock net is typically the largest contributor to on-chip power dissipation and electrical noise generation, particularly “ground bounce,” which reduces noise margin. Ground bounce is a rise in ground potential due to surges of current returning through a nonzero (typically inductive) ground path impedance. At the board and shelf level, clock distribution networks can also be a source of electromagnetic emissions, and may require considerable delay tuning for optimization of the clock distribution network.
EMC and Signal Integrity (SI)
Published in Christos Christopoulos, Principles and Techniques of Electromagnetic Compatibility, 2022
A typical problem arising in high-density high-speed circuits is shown schematically in Figure 15.13. This is an example of a single-ended signaling arrangement where the signal fed to the driver is Vin − Vref as shown. The difficulty with this arrangement is that Vref is affected strongly by parasitic components in the ground track and by fast switching currents. It is clear from this diagram that Vref ≈ L di/dt where L is the inductance associated with the ground track and di/dt is the rate of change of the current. This current is due not only to the particular driver but also to all other driven lines. Moreover, other drivers that are not driven will experience a shift in their reference level. This is described as “ground bounce” and is the source of noise and interference in high-speed circuits. This situation is familiar to EMC engineers and was described in connection with grounding in Section 10.3. Another example is shown in Figure 15.14. A similar effect is observed in connection with the supply rails, the so-called “supply bounce.” Since in modern circuits several gates switch simultaneously, the current flow and therefore the bounce in shared paths can be considerable. A more complex example is shown in Figure 15.15. Here gate 1 drives gate 2 through an interconnect. We have marked out the current path when gate 1 makes a high-to-low transition and also when it makes a low-to-high transition. We see that the parasitic inductance of the power, signal, and ground tracks will generate undesirable voltage drops at one or both of the transitions. Remedies to this situation are the reduction to the magnitude of the switched current (smaller di), increase in transition time (larger dt), reduction of the parasitic inductances (wider traces or a better transmission line configuration), or the addition of decoupling capacitors strategically placed to supply pulse current locally without the need for the pulse current to come from afar. Two such decoupling capacitors are shown in Figure 15.15. The placement of these capacitors must be chosen based on a clear understanding of the required current flows and paths so that pulsed current is supplied locally and thus voltage drops along long interconnects are minimized. It should also be borne in mind that capacitors are not ideal components and that they include a parasitic inductive component (mostly due to their lead connections). The presence of this inductance negates to some extent the beneficial impact of the capacitance in supplying pulse current while maintaining a constant voltage. At high frequencies there may also be resonances between these stray inductances and capacitances, further complicating the proper design of the circuit. The general rule of thumb is to select decoupling capacitors with low inductance value (high resonance frequency), very short lead connections to pins (preferably of surface mount technology), and typically of value 0.001 μF per module. Bulk tantalum electrolytic capacitors of a value ten times larger than the total value of decoupling capacitors are also placed around the board to provide an additional reservoir of energy for supplying current at a slower rate.
Populated power plane for wideband switching noise mitigation using CSRRs
Published in International Journal of Electronics Letters, 2021
Mohammed M. Bait-Suwailam, Akram Alomainy, Omar Ramahi
Power/ground planes are very essential in the construction of power distribution network for high-speed electronic circuits and sub-systems. Such planes are expected to deliver clean power. However, due to sudden fluctuations in switching of integrated components and circuits, for instance, transistors (Senthinathan et al., 1994; Smith, 1997), those fluctuations cause a voltage glitch, also known as simultaneous switching noise (SSN), or ground-bounce. This kind of noise was not profound in the past, due to the slow rise/fall time of the switching processors. However, with recent rapid growth in electronics and high-speed circuits manufacturing, SSN can severely degrade performance of high-speed circuits and packages. As such, proper design guidelines and precautions are needed by EMC engineers.