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Application-Specific Integrated Circuits
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
M. Michael Vai, William S. Song, Brian M. Tyrrell
The advantage of a full-custom design is that it allows the designer to fully control the circuit layout so that it can be optimized. However, these benefits only come at the cost of a very high design complexity, and thus a very high design cost. The full-custom design approach is thus usually reserved for small circuits such as the library cells to be described below, and the performance-critical part of a larger circuit. In some cases when a circuit such as a microprocessor is to be mass-produced, it may be worth the many man-months necessary to lay out a chip with a full custom approach to achieve optimized results. Full-custom design examples will be shown at the end of this chapter.
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Published in Wai-Kai Chen, Computer Aided Design and Design Automation, 2018
In a hierarchical design of circuit each block in full-custom design may be very complex and may consist of several subblocks, which in turn may be designed using the full-custom design style or other design styles. It is easy to see that because any block is allowed to be placed anywhere on the chip, the problem of optimizing area and interconnection of wires becomes difficult. Full-custom design is very time consuming; thus, the method is inappropriate for very large circuits, unless performance is of utmost importance. Full-custom is usually used for the layout of microprocessors.
Introduction
Published in M. Michael Vai, Vlsi Design, 2017
The advantage of a full-custom design is that it allows the designer to fully control the circuit layout so that it can be optimized. However, these benefits only come at the cost of a very high design complexity. The full-custom design approach is thus usually reserved for small circuits such as the library cells to be described below, and the performance-critical part of a larger circuit. In some cases when a circuit such as a microprocessor is to be mass-produced, it may be worth the many man-months necessary to lay out a chip with a full-custom approach to achieve optimized results.
A Novel Design of 12-bit Digital Comparator Using Multiplexer for High Speed Application in 32-nm CMOS Technology
Published in IETE Journal of Research, 2022
D. N. Mukherjee, S. Panda, B. Maji
Power consumption, speed and area are the three fundamental parameters to optimize the overall performance of a CMOS comparator design [10]. However, those parameters struggle with each other i.e. each individual parameter can’t be optimized independently [11]. Two-bit digital comparator has been designed with the aid of Anjuli [12] the use of 40 T PTL logic style. It provides less PDP than other logic styles. Two- bit digital comparator has been designed with the aid of Shekhawat et al. [8] the use of 26 T PTL logic style. It provides less PDP and transistor count than GDI logic styles. One-bit digital comparator has been designed with the aid of Anjali and Pranshu [13] the use of four 10 T GDI full adder cells. Hassan and Mehra [14] has 1-bit CMOS comparator using three different approaches. The full-custom-based design consumes less power and takes less area than autogenerated and semicustom design. The proposed multiplexer-based two-bit comparator consisted of 18 T which is less when in comparison with the other comparator (two-bit) designs using CMOS, PTL and TG logic technique.