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Instruments and measurement
Published in Stephen Sangwine, Electronic Components and Technology, 2018
The digital output from the Schmitt trigger circuit is connected to a counter (for frequency measurements) or a frequency divider (for period measurement). The counter is connected to a digital display so that the displayed value from one measurement can be held while the next measurement is in progress. This is important because high precision measurements can take several minutes. In modern instruments some of the functions may be implemented in software running on a microprocessor or microcontroller, including the driving of the display. A digital frequency divider consists of a counter clocked by the signal to be divided. Division by powers of 2 is easily achieved with a binary counter, but other ratios are possible.
Digital Circuit Design with Very-High-Speed Integrated Circuit Hardware Description Language
Published in A. Arockia Bazil Raj, FPGA-Based Embedded System Developer's Guide, 2018
For example, if we want to convert a 4-MHz (4,000,000-Hz) signal into a 4-Hz signal, as per Equation 2.12, scale factor = (4,000,000/2 × 4) = (4,000,000/8) = 500,000. This means that at the moment the counter value reaches 500,000, the comparator sends a reset signal and complement sign to the counter and inverter, respectively. Hence, the counter resets its value to 0 and the inverter toggles its output. These operations happen once in every 500,000 onboard clock pulses, that is, eight times within a second; thus, the frequency of clk_out is 4 Hz. In this way, just by assigning the appropriate scale factors, we can derive any frequency from the onboard clock rate. Thus, the frequency divider is a simple component whose objective is to reduce the input frequency.
Frequency Synthesis for Multiband Wireless Networks
Published in Krzysztof Iniewski, Wireless Technologies, 2017
John W. M. Rogers, Foster F. Dai, Calvin Plett
Frequency dividers consist of switching logic circuits, which are sensitive to the clock timing jitter. The jitter in the time domain can be converted to phase noise in the frequency domain. Time jitter or phase noise occurs when rising and falling edges of digital dividers are superimposed with spurious signals such as Johnson noise and flicker noise in semiconductor materials. Ambient effects result in variation of the triggering level due to temperature and humidity. Frequency dividers generate spurious noise especially for high-frequency operation. Dividers do not generate signals, but rather simply change their frequency. Kroupa provided an empirical formula, which estimates the amount of phase noise that frequency dividers add to a signal [8,9]: φDiv−Added2(Δω)≈10−14±1+10−27±1ωdo22π⋅Δω+10−16±1+10−22±1ωdo2π
Design and analysis of 73-106 GHz CMOS injection-locked frequency divider
Published in International Journal of Electronics, 2021
Yo-Sheng Lin, Kai-Siang Lan, Chih-Wei Wang
Due to the swift process of CMOS technologies, it has become possible to use them to design and implement millimetre-wave (mm-wave) integrated circuits and systems (Razavi, 2004; Y. S. Lin et al., 2010, 2012; Yeh & Chang, 2012). In frequency synthesiser or phase-locked loop (PLL) design, the first-stage frequency divider is a critical block, which converts the output signal of the mm-wave voltage-controlled oscillator (VCO) to a lower frequency (1/2, 1/3 or 1/4 of the VCO frequency) with high output power and low phase noise (Y. S. Lin et al., 2018). To cover the frequency shift of the VCO due to the process variation, a wide frequency locking range is required for the first-stage frequency divider. To drive the following frequency dividers, high output power is also essential for the first-stage frequency divider. The main design considerations for the first-stage frequency divider include power consumption, operation frequency, frequency locking range, input sensitivity, output power and phase noise.
Low spur frequency synthesiser using randomly shifted reference spur to higher frequencies
Published in International Journal of Electronics, 2020
Sakineh Jahangirzadeh, Amir Amirabadi, Ali Farrokhi
The programmable frequency divider is composed of a current mode logic (CML) divider circuit dividing by 2, a differential to the single-ended circuit, a multi-modulus divider and a divide by 2 true single-phase clock (TSPC) divider. The divide by 2 CML circuits is shown in Figure 7. Since the output of the CML circuit is differential, the signals need to be converted to single-ended for subsequent processes. Therefore, a differential to single-ended is used.