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Smart Antenna System Architecture and Hardware Implementation
Published in Lal Chand Godara, Handbook of Antennas in Wireless Communications, 2018
In a typical frequency synthesizer circuit, the output of a voltage-control oscillator (VCO) is controlled in a phase-lock loop (PLL) so that its frequency remains locked to a multiple of the frequency of a known reference. The basic principle of the PLL frequency synthesizer is quite straightforward. In the feedback path of the loop, a signal whose frequency is a suitable submultiple of the VCO frequency is generated and compared with the reference signal via a phase comparator. If their frequencies are different, the error voltage from the phase comparator forces the VCO frequency to change in such a way that this frequency difference eventually is reduced to zero. The phase comparator may be a mixer, and the reference signal may be from a crystal oscillator. With this scheme, the output frequency is a multiple of the reference frequency, and the noise performance depends on the loop configuration, the phase detector technology, and the noise characteristics of the reference signal. In particular, the noise from the reference is multiplied in the output by the ratio of the VCO frequency over the reference frequency. This is important, because in a smart antenna a very low phase noise would be required. The most extensively used PLL synthesizer architecture is the single-loop PLL. Because these devices are simple, have low cost, and are easily implemented in integrated circuits, PLL frequency synthesizers are attractive. Description of the theory and design of PLL frequency synthesizers may be found in some of the references cited earlier.16–17
Frequency Synthesizer
Published in Kaixue Ma, Kiat Seng Yeo, Low-Power Wireless Communication Circuits and Systems, 2018
Nagarajan Mahalingam, Kaixue Ma, Kiat Seng Yeo
The frequency synthesizer is typically an electronic device that can generate multiple frequencies from a single reference frequency The choice of the frequency synthesizer architecture is exhaustive and is dependent on the application requirement. The frequency synthesizer can be either analog or digital and is broadly classified as direct and indirect synthesizers based on the circuit architecture for frequency generation. In the direct frequency synthesizerst the output is synthesized by continuous mixingt multiplicationt and division of the single reference signal [1]. However achieving the spectral purity is an issue due to the existence of the spurious components and the synthesizer can be power hungry and bulky due to the large number of components. In comparisont the indirect frequency synthesis using phase-locked loops (PLL) is more popular frequency synthesizer architecture. In the PLL-based frequency synthesizer the output frequency is generated by phase locking the voltage- controlled oscillator (VCO) phase to the reference phase. Thereforet PLL-based indirect frequency synthesizers are the most preferred architecture for high-frequency applications with low power consumption. In additiont all the components in the frequency synthesizer can be integrated in any low-cost IC processes and are highly area efficient. In the remainder of this chapter we will focus in-depth on the implementation of PLL-based frequency synthesis.
System-on-a-Chip Design and Verification
Published in Nihal Kularatna, Electronic Circuit Design, 2017
Frequency synthesizer, which consists of a voltage controlled oscillator and a feed back loop, generates pure high-frequency carriers at wanted frequencies. Since voltage controlled oscillators are susceptible to the phase noise, there have been a lot of work to reduce the phase noise. A careful design of a CMOS oscillator allows the phase noise to be comparable with the bipolar transistor oscillators. Also new architectures were introduced for larger tuning range and smaller chip size. The modulus control in the loop allows selecting a wanted frequency. Integer N architecture has integer modulus of the divider in the loop. In this case, the loop bandwidth is limited because the input reference frequency must be equal to the channel spacing. In fractional N synthesizers, the output frequency can vary by a fraction of the input frequency, allowing the latter to be much greater than the channel spacing. Recently introduced all digital phase locked loops (ADPLL) meet most of these requirements.
Design and analysis of 73-106 GHz CMOS injection-locked frequency divider
Published in International Journal of Electronics, 2021
Yo-Sheng Lin, Kai-Siang Lan, Chih-Wei Wang
Due to the swift process of CMOS technologies, it has become possible to use them to design and implement millimetre-wave (mm-wave) integrated circuits and systems (Razavi, 2004; Y. S. Lin et al., 2010, 2012; Yeh & Chang, 2012). In frequency synthesiser or phase-locked loop (PLL) design, the first-stage frequency divider is a critical block, which converts the output signal of the mm-wave voltage-controlled oscillator (VCO) to a lower frequency (1/2, 1/3 or 1/4 of the VCO frequency) with high output power and low phase noise (Y. S. Lin et al., 2018). To cover the frequency shift of the VCO due to the process variation, a wide frequency locking range is required for the first-stage frequency divider. To drive the following frequency dividers, high output power is also essential for the first-stage frequency divider. The main design considerations for the first-stage frequency divider include power consumption, operation frequency, frequency locking range, input sensitivity, output power and phase noise.
Low spur frequency synthesiser using randomly shifted reference spur to higher frequencies
Published in International Journal of Electronics, 2020
Sakineh Jahangirzadeh, Amir Amirabadi, Ali Farrokhi
A frequency synthesiser plays a major role in RF transceivers. An Integer-N frequency synthesiser is utilised to create a set of frequencies which are integer multiplicand of a reference frequency. The Integer-N frequency synthesiser consists of a phase-frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider in the feedback path. A PFD compares the phase and frequency between the input reference signal and the divider output signal. It then produces an error signal which triggers the CP to vary the amount of pumped charge to the LPF. The LPF provides a smooth voltage proportion to PFD outputs to drive the VCO control voltage setting an output frequency. The loop continues the process until the phase difference between the input reference signal and the feedback signal is zero or constant that is the locked state.