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Circuits for Clock Signal Generation and Synchronization
Published in Tertulien Ndjountche, CMOS Analog Integrated Circuits, 2017
In operation, the prescaler logic block of each 2/3 counter first divides the frequency of the incoming signal, Fi, and the resulting signal, F0, is applied to the following counter cell. The division ratio is determined by the logic state of the control signals applied to the end-of-cycle logic block of each 2/3 counter cell. Upon completion of a division cycle, the end-of-cycle logic block of the last 2/3 counter cell in the divider chain generates a signal, Mod0, which is transferred successively to the preceding 2/3 counter cells after being retimed by each cell. The division cycle corresponds to the clock period of the F0 signal available at the output of the last 2/3 counter, whose Mod0 terminal can serve as the divider output. To avoid the perturbation of the current division operation, the updated control signals for the division ratio should transit through latches, which are synchronized with the respective division cycle, on their way to each 2/3 counter cell. A new division ratio can be set only when a division cycle is completed.
RF Communication Circuits
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
Michiel Steyaert, Wouter De Cock, Patrick Reynaert
Several structures can be used as programmable divider. Programmable counters are the easiest solutions and are available in standard cell libraries. They are, however, limited in operation frequency. When high frequencies need to be synthesized, one can use a so-called prescaler. A prescaler divides by a fixed ratio and can therefore operate at high frequencies because they do not have to allow for delays involved with counting and presetting. A few high speed prescaller stages lower the speed used in the following counter stages. The disadvantage is that for a certain frequency resolution, the reference frequency has to be lowered. This slows the loop down as a lower bandwidth has to be implemented to maintain stability in the loop. A solution to this resolution problem is the use of dual- or multi-modulus prescalers. This circuit extends the prescaler with some extra logic to allow the prescaler to divide by N and N + 1 in case of a dual-modulus prescaler and by N to N + x in case of a multi-modulus prescaler. The speed decrease of this extra circuitry can usually be kept limited. Figure 4.13 shows two possible implementations of a dual-modulus prescaler. Implementation given by Figure 4.13a is a straightforward implementation based on d-flipflops. The critical path consists of a NAND gate and a d-flipflop. Implementation given by Figure 4.13b is a more complex implementation. It is based on the 90° phase relationship between the outputs of a master/slave toggle flipflop. It contains no additional logic in the high frequency path. The dual-modulus prescaler is as fast as an asynchronous fixed divider.
Timers and Counters
Published in Julio Sanchez, Maria P. Canton, Embedded Systems Circuits and Programming, 2017
Julio Sanchez, Maria P. Canton
The rightmost multiplexer symbol depicts the control of the prescaler function. The prescaler serves as a frequency divider for the signal and allows slowing down the clock action on Timer0. As shown in Figure 11-1, the control bit for the prescaler function is bit 3 of the OPTION register, labeled PSA. If this bit is clear, the prescaler is assigned to the Timer0 module. If the PSA bit is set, then the prescaler is assigned to the Watchdog timer. Bits 0, 1, and 2 of the OPTION register define eight possible prescaler settings.
A fully integrated 2TX–4RX 60-GHz FMCW radar transceiver for short-range applications
Published in International Journal of Electronics, 2023
Dušan P. Krčum, Đorđe P. Glavonjić, Veljko R. Mihajlović, Lazar V. Saranovac, Vladimir M. Milovanović, Ivan M. Milosavljević
To linearize a VCO tuning curve as well as to generate the FMCW chirp, a fractional-N PLL, depicted in Figure 4, is employed. Since in the simplest homodyne FMCW radar implementations the local oscillator (LO) signal is split and shared between the TX power amplifier (PA) and the RX mixer, the fundamental VCO topology Kang et al. (2011) is chosen. The feedback divider consists of a constant divide-by-4 prescaler, and a five-stage variable multi-modulus divider (MMD) providing a 48-to-79 division ratio. An additional auxiliary divider is used to obtain scaled signal. The PLL uses a conventional phase-frequency detector (PFD) to compare a fixed 240-MHz reference frequency, which also drives the on-chip FMCW generator, with the divided feedback.
A 40-nm low-power WiFi SoC with clock gating and power management strategy
Published in International Journal of Electronics, 2023
Han Su, Jianbin Liu, Yanfeng Jiang
The PLL module includes a frequency doubler, a prescaler, a phase frequency detector (PFD),a charge pump (CP), a loop pass filter (LPF) and a voltage-controlled oscillator (VCO). For reducing the PLL’s output noise, a frequency doubler shown in Figure 5 is used to change the reference clock from 40 MHz to 80 MHz. It consists of a XOR gate and a clock delay line for producing the double-frequency clock and controlling the clock’s duty cycle. The frequency doubler contains a bypass path so that PLL can also support 40 MHz clock as its reference. The PFD and CP use the conventional architecture. The third-order passive LPF is also shown in Figure 5. The transfer function is represented as:
4.02-5.48 GHz wideband VCO with coupling reduction and small Kvco variation
Published in International Journal of Electronics, 2020
Wei Zou, Daming Ren, Kefeng Zhang, Xuecheng Zou
The measured tuning range is illustrated in Figure 9 and the frequency varies from 4.02 to 5.48 GHz with changes from 0.3 to 1.5 V, which is highly matching with the simulated result of 4.05–5.52 GHz and satisfies the requirements of the standards in Table 1. The effectiveness of the proposed varactor group is verified in Figure 10(a). The value of is measured to be 1.22, and an excellent tuning linearity is achieved except at the edge of . Since overlap regions exist between adjacent sub-bands, the in the fine-tuning process is constant. Figure 10(b) plots the variation over different sub-bands with a certain of 0.9 V. The variation is 53.6% in conventional VCO design, and the variation is decreased to 6.0% by using the extra 3-bit switched varactor array in simulation. The measured is from 54.1 to 60.9 MHz/V, which corresponds to a variation of 5.9%. A small variation is beneficial to the optimal design of lock time, phase noise, and loop characteristics in PLLs. The measured phase noise at the centre frequency of 4.75 GHz is plotted in Figure 11, which is proven to be −121.6 dBc/Hz at 1 MHz offset. The phase noise at 1 MHz offset within the whole frequency range of 4.02–5.48 GHz is shown in Figure 12 and the phase noise is less than −119.8 dBc/Hz. The phase noise can be less than −125.8 dBc/Hz after the divide-by-two prescaler in the FS since the divider with a division ratio of N can reduce the phase noise by 20log(N), which is better than −121 dBc/Hz and thus meeting the requirements of the standards in Table 1. The current consumption changes from 4.3 to 8.8 mA. The realised 4.02–5.48 GHz frequency range and low phase noises satisfy the requirements of the major wireless communication standards, such as Bluetooth, WLAN 802.11 b/g, TD-SCDMA, WCDMA, LTE and so on. Table 4 shows the performance summary and compares it with recently published state-of-the-art small variation VCOs. The proposed VCO is proven to achieve a better figure of merit (FoM) compared with the VCOs presented in Kong et al. (2017), Xu et al. (2016), and Jin et al. (2014), as well as realise a low phase noise and an effective optimisation in the variation. The VCO in (Z. Liu et al., 2019) achieves a FoM performance that is 3.9 dB better than that of the proposed VCO; however, the circuit is designed using a 55 nm technology and it is believed that the performances, e.g., power consumption, can be effectively optimised if a finer CMOS technology is employed. Moreover, the proposed VCO with an 8-shaped inductor realises higher insensitivity to interference aspects and better isolation compared with the VCOs previously reported.