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Digital Electronics
Published in Walter Fox Smith, Experimental Physics, 2020
This counting scheme can be extended to count up to any power of 2 that you like. Using three latches you can build a counter with eight states that can count from 0 to 7. With four latches you have 16 states and can count from 0 to 15 and so on. This kind of counter, where the output of one stage is used as the clock input for the next stage, is called a ripple counter because of the way information ripples along from one stage to the next. The problem with this kind of counter is that, since the clock for one stage is the output from the previous stage, it takes time for changes to propagate through the whole counter and during the brief interval that the change takes there are unwanted, incorrect glitch states present on the outputs. The next section will show how to eliminate these glitch states and will produce a method of designing more general sequential circuits than simple counters.
Circuit Components
Published in Julio Sanchez, Maria P. Canton, Microcontroller Programming, 2018
Julio Sanchez, Maria P. Canton
The 74193 is a synchronous counter, so its output changes precisely at each clock pulse. This is convenient since it allows connecting its output to other logic gates and avoids the glitches associated with ripple counters. Note from Figure 6-21 that the 74194 has separate clock inputs for counting up and counting down. The count increases as the up clock input becomes high (on the rising-edge). The count decreases as the down clock input becomes high (on the rising-edge). In both cases the other clock input should be high. For normal operation the Preset input should be high and the Reset input low. When the Reset input is high it resets the count to zero, that is, lines QA to QD are low. The counter can be preset by placing any desired binary number on inputs A to D and making the Preset input low. These inputs may be left unconnected if not required.
Logic Gates and Circuit Components
Published in Julio Sanchez, Maria P. Canton, Embedded Systems Circuits and Programming, 2017
Julio Sanchez, Maria P. Canton
The 74193 is a synchronous counter so its output changes precisely at each clock pulse. This is convenient because it allows for connecting its output to other logic gates and avoids the glitches associated with ripple counters. In Figure 3-22 you can see that the 74193 has separate clock inputs for counting up and counting down. The count increases as the up clock input becomes high (on the rising-edge). The count decreases as the down clock input becomes high (on the rising-edge). In both cases the other clock input should be high. For normal operation the preset input should be high and the reset input low. When the reset input is high, it resets the count to zero, that is, lines QA to QD are low. The counter can be preset by placing any desired binary number on inputs A to D and making the preset input low. These inputs may be left unconnected if not required. Several 74193 counters can be chained by wiring a common reset line, connecting the carry to the up clock line of the next counter and the borrow to the down line.
Design of CNTFET-based Ternary Ring and Up–Down Counter Cells
Published in IETE Journal of Research, 2023
Trapti Sharma, Anil Kumar Sahu, Himanshu Shekhar, Hemlata Shakya
Counters are crucial processing elements in several VLSI applications such as ADCs/DACs, frequency dividers, timers, memory, and other consumer electronic devices. The primary input that is applied for the operation of the counter circuit is the clock input; therefore, designing reliable counter circuits consuming less power and energy consumption is of prime importance. The fact is that in counter designs more than 40-45% of the power consumption is contributed by applied clock input of individual flip-flop stages irrespective of its on/off status [8]. Therefore, the ternary logic benefit of increased computational capability can be utilized here which results in increased interconnect complexity for digital designs [9]. For instance, consider a synchronous mod-25 counter realization. If binary logic is utilized for implementation, five flip-flops are needed for the counter design where five clock inputs are required. On the other hand, if ternary logic is employed, then 3-stage or 3-flip-flops (3-clock inputs) are sufficient to realize the same. So far, three-valued logic counter structures, a reduction in clock signals up to 40% is obtained which in turn leads to a further reduction in power consumption and improvement in energy efficiency as well. Therefore in this work, a ternary logic advantage of increased data density is exploited for the realization of increased functionality within the same module.
An area efficient, high-frequency digital built-in self-test for analogue to digital converter
Published in International Journal of Electronics, 2018
M. Senthil Sivakumar, S. P. Joy Vasantha Rani
In DNL-based test architecture, the BIST controller sets the LSB counter to count from 0 to 2N−1 with reset and clock control. The counter counts the step size of the digital code between two successive code transitions. The logic high value of the transition resets the counter to the initial position. The counter measures the step size of the digital code between two adjacent transition points through the clock controlled counts. The maximum count in the LSB counter has considered as a step size of the digital code, Tstepsize. The divergence in counter steps size Tstepsize from the ideal step size is measured to identify the transition width fault. Presence of transition step size error is projected through the difference block as follows.
Ideas for Improving the Digital Design Lab
Published in IETE Journal of Education, 2023
Synchronous counters can be designed using JK, D, or T flip-flops. The minimum number of flip-flops required to build a synchronous counter is log2n, where n is the number of states. A counter can be a binary up/down counter [10,13], or a counter that generates a specific sequence. A binary up-counter of k bits will generate the sequence {0, 1, 2, … , 2k–1}. A modulo-m counter generates the sequence {0,1,2, … ,m−1}. A modulo-10 counter is also called a decade counter. An example of a 3-bit sequence generator is a circuit that generates the sequence {0, 1, 3, 2, 4, … }.