China
Africa
Explore chapters and articles related to this topic
Packaging Issues for SiGe Circuits
Published in John D. Cressler, Circuits and Applications Using Silicon Heterostructure Devices, 2018
Kyutae Lim, Stephane Pinel, Joy Laskar
Advantages of flip chip include efficient die access, high assembly yields using solder attachment, elimination of an interconnect layer, lower inductance, and the potential for low cost. Efficiency of die access comes from the fact that the entire surface of the die is available for electrical connection (as opposed to just the edges in wire bonding.) Using solder attachment, instead of conductive adhesives, provides the possibility of high assembly yields due to the self-alignment properties of the solder. The wire bond is eliminated, providing higher reliability by reducing one level of interconnect. The removal of the “long-lead” wire bond also reduces the inductance, an important feature for RF applications. The opportunity for low cost comes from the fact that flip chip is created at the wafer level. This cost savings is only realizable with a well-understood, controlled, efficient assembly process.
3D Interconnects with IC's Stack Global Electrical Context Consideration
Published in Thomas Noulis, Noise Coupling in System-on-Chip, 2018
Yue Ma, Olivier Valorge, J. R. Cárdenas-Valdez, Francis Calmon, J. C. Núñez–Pérez, J. Verdier, Christian Gontrand
Chips can also be stacked vertically using wire-bonding and flip-chip techniques. However, the flip-chip technique solely provides an interconnection between two chips; whereas, wire-bonding only enables the connection of chip input/output pads located at their perimeter. Moreover, wire-bonding presents disadvantages in terms of surface and propagation delays depending on the application frequency clock and the wire-bond lengths. Finally, solder balls are put on the 3D systems bottom layers backsides to ensure connection with their environment. Compared with 2D classical schemes, 3D integration potential benefits are numerous: performance improvement, flexible heterogeneous system combinations (logic CMOS, RF analog function, memories, and sensors), significantly shortened interconnect line networks that decrease interconnect line delays and power consumption (which become significant obstacles in 2D VLSI systems relative to delays in transistor switching), smaller form factors, and reduced fabrication costs [1,2].
Antennas for RFID Transponders
Published in Albert Lozano-Nieto, RFID Design Fundamentals and Applications, 2017
Direct die attachment can be achieved using two techniques: wire bonding or flip-chip. Flip-chip is a technology for interconnecting semiconductor devices by creating conductive bumps in the pads of the chip. In order to connect the chip, this has to be flipped so the bond pads are in contact with the matching pads in the circuit. In the wire-bonding technology, the chip is mounted upright and wires are used to connect the chip to the circuit. In the case of RFID transponders, the bumps or wires are connected to the antenna, thus being an ideal method to use for printed, etched, or stamped antennas. In this case, the resonance capacitor can also be etched on the substrate of the transponder, and therefore this technology does not require binding it with the chip as COB does. Figure 2.33 shows an example of this type of connection.
Optimal design of thermo-compression bonder via ANN-based surrogate modeling under uncertainty
Published in Journal of Engineering Design, 2023
Sungkun Hwang, Sang Won Lee, Hae-Jin Choi, Seung-Kyum Choi
With the great attention of microelectromechanical systems (MEMS), diverse packaging mechanisms (Li and Goyal 2020; Zhang et al. 2019; Balakrishnan et al. 2022) have been developed for 2.5- or 3-D chip stacking structures, assuring finer pitch, higher I/O density, and shorter interconnection. Under the new mechanisms, the interconnection quality becomes the primary key to guaranteeing the performance of the MEMS. When the interconnection is flawed, structural warpage or electrical short happens, prompted by a severe mismatch of coefficients of thermal expansion (CTE). Compared to previous bonding techniques, such as wire or compliant bonding (Ou et al. 2021), flip-chip technology (Su et al. 2020; Chen et al. 2019; Zhang et al. 2022) has shown yield superiority regarding ultra-fine pitch, short interconnection, and higher reproducibility. However, unfortunately, the flip-chip mechanism still poses serious issues, such as excessive thermal vulnerability that triggers structural warpage or crack propagation. To handle the thermal-structural issue, a promising method, namely TCB, has been developed (Li et al. 2019; Park and Kim 2020; Chauhan et al. 2014; Sun et al. 2020; Bonam et al. 2019).