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Gigabit Mobile Communications Using Real-Time MIMO-OFDM Signal Processing
Published in George Tsoulos, MIMO System Technology for Wireless Communications, 2018
Volker Jungnickel, Andreas Forck, Thomas Haustein, Christoph Juchems, Wolfgang Zirwas
However, these three steps (read, add/subtract, write) must be performed consecutively, which needs a higher clock in the channel estimator than for other sample rate operations. To avoid this higher clock, the circuit is actually implemented as a wrapped pipeline using a dual-port RAM and an adder as shown in Figure 11.4. At first, the scrambling is reversed and the signal is either added to or subtracted from the last intermediate result. The latter is recalled from port 1 of a dual-port RAM, and the result is stored in port 2. The idea is then to exchange the two-port address spaces for read and write operations from training symbol to training symbol, where the address of each subcarrier is used once in each address space and counted through by the carrier index n. All processes are organized in this wrapped pipeline so that the read, add or subtract and write tasks are effectively performed in a single cycle. We have operated 4 · nTx · nRx = 60 of these circuits in parallel at 100 MHz in the experimental system. This highly parallel channel estimator operates very reliably, even in complex FPGA designs. We like to point out that the realization of the channel estimator using the wrapped pipeline was one of the key ideas for stable operation of the entire MIMO-OFDM signal processing core at 100 MHz clock.
In-Phase and Quadrature-Phase Sinusoidal Signal Generation Using DDS Technique
Published in IETE Journal of Research, 2021
Alfred Vivek D’Souza, D. J. Ravi
The LUT is implemented as a dual port distributed read only RAM. The data stored inside a dual port RAM are accessed twice in same cycle. This is utilized to output one sample of sine and cosine waves each in the same cycle. Eighteen bit 2:1 MUX is used for 1’s complementing indices or address of RAM and eight-bit 2:1 MUX is used for 1’s complementing sine and cosine output amplitude values. The input signals “sclk,” “sdata,” and “update” are used to feed the value of frequency control word M serially to the FPGA.