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The Driving Forces Behind Moore’s Law and Its Impact on Technology
Published in Lambrechts Wynand, Sinha Saurabh, Abdallah Jassem, Prinsloo Jaco, Extending Moore’s Law through Advanced Semiconductor Design and Processing Techniques, 2018
Lambrechts Wynand, Sinha Saurabh, Abdallah Jassem
The rate of technological advancement as a function of time is governed by the correlation by which the number of components in very large-scale integration (VLSI) integrated circuits (ICs) and their total computing power double approximately every 18–24 months (Moore 1965;Hutcheson 2009). This phenomenon is known as Moore’s law, and was predicted in a 1965 paper by Gordon Moore (Moore 1965), the co-founder of Fairchild Semiconductor and Intel. Moore predicted that the quantity of components integrated into ICs would increase twofold each year for the next decade (from 1965), and ten years later (during 1975), adjusted the prediction to the integrated components doubling every two years. This held true up until the current decade (five decades later), with deviations only occurring recently in response to several factors, primarily physical limitations (at atomic level) and changes in computing habits (such as multicore and open-hardware systems). In 2009, IBM Fellow Carl Anderson noted a trend of semiconductor technology maturing and exponential growth slowing down, similar to that of the railroad, the automotive industry and aviation before it. Moore’s law is related to the scaling law founded on the work of Dennard (1974), known as Dennard scaling. Dennard scaling is specifically related to power scaling in complementary metal-oxide semiconductor (CMOS) transistors. Essentially, the Dennard scaling law states that the overall IC power consumption for a set area – therefore, the power density – remains constant if the feature size (node) of the technology scales downward, typically by a decreasing gate length. Dennard (1974) provides scaling results for circuit performance, which have been adapted and are presented in Table 1.1.
Nanowire Transistors: A Next Step for the Low-Power Digital Technology
Published in IETE Journal of Research, 2021
D. Ajitha, K. N. V. S. Vijaya Lakshmi, K. Bhagya Lakshmi
Dennard scaling rules indicate that the power consumption is effectively reduced by scaling the dimensions and operating voltages [55]. Furthermore, the research on scaling devices shows that the vertical SiNW is a promising device for low-power applications [56] and the optimized digital circuits also prove the same [57]. The major goal of fabricating NWT with various technologies and scaling down nanowire transistors is use them in electronic circuits in ICs with lower power consumption. Based on these two ideas, a new measurement perception factor, device integration factor (DIF), is proposed [16]. DIF factor can integrate transistors into ICs and it is inversely proportional to the channel power dissipation (Wch) and channel area (Ach). DIF value is calculated for the existing fabrication technologies and it is concluded that the best nanolithography technique is atomic force microscope (AFM). AFM is the best suitable method for fabricating the SiNW in future ICs.