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Self-Driven Clock Gating Technique for Dynamic Power Reduction of High-Speed Complex Systems
Published in Durgesh Nandan, Basant K. Mohanty, Sanjeev Kumar, Rajeev Kumar Arya, VLSI Architecture for Signal, Speech, and Image Processing, 2023
Roopa R. Kulkarni, S. Y. Kulkarni
The clock gating logic works on the principle of gating the nonfunctional logical unit or nonfunctional high-performance latches from the clock input. This technique can be applied at all levels: system level, architectural design, logic as well as gate-level [2, 3]. The techniques to reduce the dynamic power using clock gating along with the advantages are described in Refs. [4, 6]. The clock signal can be either gated to a latch or a logical gate by ANDing the clock input with a control signal. Hence, preventing the redundant charging/discharging of the capacitances when the circuit is idle. This helps in saving the circuit’s clock power. Fundamentally, there are two basic types of clock gating, latch free and latch-based clock gating. The latch free clock gating technique uses an AND based logic, wherein the input to the AND gate is the enable signal and the clock input. The clock is gated when the enable input is low and is transparent when the enable input is high. The drawback of this is that it leads to the generation of glitches, which leads to uncertainty in the gated clock output. To overcome this major drawback a latch-based clock gating is used. In this technique, the gated clock output is obtained from the latch and the AND gate. The latch will hold the enable input till the clock input and hence overcomes the glitch problem. The other flavor of the architectural clock gating techniques are: data-driven CG, look ahead CG, self XORed CG, etc.
Design for Low Power
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
Hai Li, Rakesh Patel, Kinyip Sit, Zhenyu Tang, Shahram Jamshidi
A widely used technique in the industry for dynamic power reduction is clock gating. Since usage of functional blocks in design is highly dependent on the application used [5], there are opportunities to shut off circuits that are not used all the time. In turn, this will result in switching power savings. Figure 12.4 illustrates the mechanics of clock gating. Clock gating is achieved by ANDing the clock with a gated-control signal (enable). This enable will shut off the clock to the specific circuit when it is not used, thus avoiding unnecessary toggling of circuit and all the associated capacitances. A specific area that clock gating aims for is sequential elements and local clock drivers. Figure 12.3 illustrates that 33% and 32% of total clock power are consumed by local clock drivers and sequential elements, respectively.
Digital Systems
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
Festus Gail Gray, Wayne D. Grover, Josephine C. Chang, Bing J. Sheu, Roland Priemer, Rung Yao, Flavio Lorenzelli
By “clock gating,” we mean selectively removing or masking active phases or edges from the clock signal at one or more latches. One valid reason to gate the clock in CMOS is to reduce power consumption. Many circuit designs possess large modules or subsystems which it makes sense to stop cycling in certain application states. Gating the clock off is therefore the simplest form of power management, because CMOS has negligible power dissipation in a static state. However, even for this simple use of clock gating, the main issue is avoiding glitches when gating the clock.
Power optimisation of single phase clocked feedback D flip-flop for CDMA
Published in International Journal of Electronics Letters, 2022
Efforts are made in this paper to reduce power with optimum delay and area. Since power is reduced at the cost of delay and delay is optimised at the cost of area. In this work, design is adopted which gives best tradeoff between power, delay and area. Flip-flop is optimised for all possible ways of clock gating. This flip-flop is tested for minimum PDP with optimum area in terms of number of transistors. Generally, clock gating is done by XOR and AND logic. In this paper, logic is designed by proposed GDI cell with logic. Section 1.1 and 1.2 describes MTCMOS and clock gating, respectively. Section 2 justifies basic GDI cell and proposed GDI cell. Section 3 explains single phase clocked feedback D flip-flop with proposed clock gating techniques. Results are discussed in section 4. Conclusion is highlighted in section 5.
Hybrid buffers based coarse-grained power gated network on chip router microarchitecture
Published in International Journal of Electronics, 2020
Yogendra Gupta, Lava Bhargava, Ashish Sharma, M.S. Gaur
With the advancement of semiconductor technology, the circuit designers constantly trying to reduce dynamic and static power consumption. Clock gating and power gating are the most used techniques to minimize dynamic and static power respectively (Hu et al., 2004). Some researchers proposed novel clock gating schemes by incorporating leakage control transistor which simultaneously minimizes static and dynamic power ‘(Majumder & Bhattacharjee, 2018)’. Jafari et al. proposed a power gating technique in different level of hierarchy while designing the cache memories using a SRAM cell. The hierarchical levels SRAM based cache design include cell, row, bank and entire cache memory in 16 nm FinFET (Fin Field Effect Transistor)(Jafari, Imani, & Fathipour, 2015)’. In recent years power and energy issues of Network on Chip has been explored by the research community. Recently Mirhosseini et al. ‘(Mirhosseini et al., 2015)’ proposed ‘Virtual Channel power gating techniques with traditional SRAM based buffers’. Catnap ‘(Das, Narayanasamy, Satpathy, & Dreslinskiv, 2013)’ is a coarse-grained power gating technique that turns on and off entire subnetwork which has highly asymmetric traffic patterns. Zhan et al., (2016) present a fine-grained power management scheme at the buffer level with introducing STT-MRAM based hybrid buffer. Because buffer in Network on Chip is the dominant power consumer, research community put lots of effort to reduce buffer power. Buffer-less NoC ‘(Moscibroda & Mutlu, 2009)’ is one way of saving leakage power as well as area. (wang et al., 2016) proposed a cost-effective and power efficient NoC router microarchitecture for the unidirectional torus network, and adopt an improved corner buffer structure which is used to mitigate the performance overhead incur due to power gating technique ‘(Wang, Niknam, Wang, & Stefanov, 2017)’. The bufferless NoC has performance penalties when high network load is there. STT-MRAM based hybrid cache memory has been explored in on-chip cache domain. Jang et al. ‘(Jang, An, Kulkarni, Yum, & Kim, 2012)’ first leverage STT-MRAM as a buffer in Network on Chip. Dark silicon aware Network on Chip architecture is designed in DimNOC ‘(Zhan, Ouyang, Ge, Zhao, & Xie, 2015)’ which uses STT-MRAM based buffer with flexible fine-grained power gating mechanism at a buffer level. In our work, we have proposed coarse-grained power gating techniques with STT-MRAM as a hybrid buffer for power efficient network on chip design.