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Low-Power/Energy Compiler Optimizations
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
Dynamic voltage scaling (DVS) is recognized as one of the most effective power reduction techniques. It exploits the fact that a major portion of power of CMOS circuitry scales quadratically with the supply voltage [3]. As a result, lowering the supply voltage can significantly reduce power dissipation. For noninteractive applications, such as movie playing, decompression, and encryption, fast processors reduce device idle times, which, in turn, reduce the opportunities for power savings through hibernation strategies. In contrast, DVS techniques are still beneficial in such cases (i.e., DVS reduces power even when these devices are active); however, DVS comes at the cost of performance degradation. An effective DVS algorithm is one that intelligently determines when to adjust the current frequency-voltage setting (scaling points) and to which frequency-voltage setting (scaling factors), so that considerable savings in energy can be achieved while the required performance is still delivered.
Low-Power Design for Smart Dust Networks
Published in Syed Ijlal Ali Shah, Mohammad Ilyas, Hussein T. Mouftah, Pervasive Communications Handbook, 2017
Variable voltage processors are capable of operating over a wide voltage range. Allocating such a processor for the network nodes allows power reduction by dynamically varying the supply voltage [12–15]. The method is often termed dynamic voltage scaling (DVS). DVS is an efficient method for power reduction; however, it imposes some limitations for the system: The system components must be capable of operating over a wide voltage range.A voltage converter loop hardware must be available.
Operating System Power Management
Published in S. Sitharama Iyengar, Richard R. Brooks, Distributed Sensor Networks, 2016
Vishnu Swaminathan, Krishnendu Chakrabarty
Designers of embedded processors that are used in sensor nodes now include variable-voltage power supplies in their processor designs, i.e., the supply voltages of these processors can be adjusted dynamically to trade-off performance with power consumption. Dynamic voltage scaling (DVS) refers to the method by which quadratic savings in energy is obtained through the run-time variation of the supply voltage to the processor.
Graceful degradation for reducing jitter of battery life in fault-tolerant embedded systems
Published in International Journal of Systems Science, 2018
Salim Kalla, Riadh Hocine, Hamoudi Kalla, Abderrezak Chouki
A degraded operating mode is obtained from the full mode by the relaxation of constraints, as the reduction of tasks replicas to relax reliability constraint. In such degraded mode the execution time is reduced and/or deadline is increased compared with full mode. In case of degradation, we use dynamic voltage scaling technique (DVS) to save energy. The processor is scaled to the adequate speed according to the degradation factor of the degraded mode.