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Image-Processing Architectures
Published in Edward R. Dougherty, Digital Image Processing Methods, 2020
The propagation times of IC logic gates increases by roughly a factor of 10 every decade. Computer processing power increases at a factor of 100 per decade (see Fig. 14). New high-performance serial “superscalar” architectures have been able to push ahead of the IC curves by taking advantage of higher logic density to promote concurrent operations. Internal pipelines allow the overlap of the various stages of processing instructions. Internal high-speed cache memories hold current data and instructions. Harvard architectures separate the instruction memory from the data memory so that both can be fetched simultaneously. Long instruction words allow further concurrency in processing. Branch prediction allows the instruction for the most probable branch path to be entered into the pipeline so that pipeline efficiency can be maintained.
Enhancing CPU performance
Published in Joseph D. Dumas, Computer Architecture, 2016
Branch prediction is one approach that can be used to minimize the performance penalty associated with conditional branching in pipelined processors. Consider the example presented in Table 4.2. If the control unit could somehow be made aware that instructions I1 through I4 make up a program loop, it might choose to assume that the branch would succeed and fetch I1 (instead of I5) after I4 each time. With this approach, the full branch penalty would be incurred only once (upon exiting the loop) rather than each time through the loop. One could equally well envision a scenario in which assuming that the branch would fail would be the better course of action; but how, other than by random guessing (which, of course, is as likely to be wrong as it is to be right) can the control unit predict whether or not a branch will be taken?
Pipeline Architecture
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
The branch prediction technique, on the other hand, is however, considered to fit mainly in the domain of pre-RISC culture. It regained importance when the more advanced superscalar machine, under certain compulsions due to its design philosophy, started to exploit this technique for its own convenience. Some processors, like PowerPC 601, use a simple static branch prediction technique. More sophisticated superscalar processors such as the PowerPC 620, the Pentium 4, and most other superscalar machines use the traditional dynamic branch prediction technique based on accumulated branch history analysis to improve their efficiencies.
Exploration for Software Mitigation to Spectre Attacks of Poisoning Indirect Branches
Published in IETE Technical Review, 2018
Baozi Chen, Qingbo Wu, Yusong Tan, Liu Yang, Peng Zou
When a branch instruction is executed, it may change the original increment of PC which is used immediately in the fetch stage of the next instruction in pipeline. Since the new value of PC would be determined only after the branch instruction has been decoded, there would be stalls for the next instruction to wait for the PC value of the next fetch. Branch prediction is done by the processor to try to determine where the execution will continue after a conditional jump, so that it can read the next instruction from memory without any stalls. Speculative execution goes one step further and determines what the result would be from executing the next instructions. If the branch prediction was correct, the result is used, otherwise it is discarded. A common technique to improve the efficiency of speculation is to only speculate on instructions from the most likely execution path, which means to combine with branch prediction.