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Multiplexers, Demultiplexers, ROMs, and PLDs
Published in Eugene D. Fabricius, Modern Digital Design and Switching Theory, 2017
AND-OR-INVERT (AOI) gates reduce the actual number of transistors needed for two levels of NAND or NOR logic by physically merging the logic into one level. This results in faster circuits. Also, with outputs Z and Z¯ available, both SOP and POS solutions are available at the output. The basic AOI circuit, with true and complemented outputs, is shown in Figure 6.7.
Combinational Circuits and Their Implementation
Published in Ronald C. Emery, Digital Circuits, 2020
A very useful gate is available which allows the direct implementation of SOP f type functions. This circuit is the AND-OR-INVERT (AOI) gate. The AOI is manufactured in several configurations, but all of them do exactly as the name implies: that is, an AND-OR and then an inversion action (Fig. 4.22).
TCAD performance analysis of a symmetrical double gate non-aligned junction FET device with high and low dielectric gate oxide in sub-100 nm regime
Published in International Journal of Electronics Letters, 2023
Vasu Banoth Naik, Arun Kumar Sinha
The %NA comes to be 50% giving best result for this device. SiO2 and HFO2 are used as gate oxide and are also used as spacer with 5 nm width and 2.5 nm thickness. The electrodes have thickness of 1 nm in contact from outside the device. The double gate structure is applied with the same voltage to turn on the device and invert a channel. A uniform doping junction is used in the Source and Drain regions; the regions are heavily doped with 1 × 1018 cm−3 concentration of phosphorous, and the channel is lightly doped with profile of 1 × 1010 cm−3 concentration of boron (Kumar et al., 2020). The doping concentration profile is shown in Figure 2. The device electric field is responsible by voltage applied at Gate-1 and Gate-2 placed at symmetric position. Tunnelling is the phenomena which occur because the edge of the valence band in the channel region is higher than the tip of the conduction band in the drain region. From Figure 3 it can easily be seen that the tunnelling width is more and channel’s valence band edge height is lesser than the drain’s conduction band edge for the NADGNFET device; hence, it reduces tunnelling of charge and thereby reducing the gate leakage (Kumar et al., 2020).
New theorems for inverting the functions of logic gates in digital circuits
Published in Journal of Control and Decision, 2022
Logical operations in the above context combine two or more input variables in order to perform standard logic functions of logic gates. For instance, the inputs of ‘a’ and ‘b’ can be combined together to implement AND gate. The AND operation can be represented as ‘a.b’, ‘a•b’ or ‘ab’. Similarly, the input of ‘a’ or ‘b’ can be combined together to implement the OR gate. The OR operation can be represented as ‘a + b’. Thus, it is possible to methodologically invert the inputs to certain logic gate in order to change its function to another logic gate. Moreover, there are classical theories that extended the Boolean algebra. For instance, De Morgan's theorem and Kaunaugh's maps have been proposed to further clarify the design of digital logic circuits (Brown & Vranesic, 2014). Thus, the outputs of the first and second theorems that De Morgan proposed are ‘1000’ and ‘1110’ respectively (Nehinbe, 2022). In other words, rule 1 [1000] is equivalent to (a’•b’) = (a + b)’ while rule 2 [1110] is equivalent to (a•b)’ = (a’+b’).
3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications
Published in IETE Journal of Research, 2022
Achinta Baidya, Trupti R. Lenka, Srimanta Baishya
The main advantage of the pass transistor logic circuit is reduction in the number of transistors compared to conventional CMOS circuits. Pass transistor logic-based AND gate in Figure 6 uses only two n-JNTs. Transistor number decreases by 50% compared to CMOS configuration. Again Pass transistor logic circuits have an advantage of very low power dissipation as its operation depends only on the input signal voltages and no separate power supply is required. Two-input n-JNT PTL schematics for AND and OR gates, along with truth tables, are shown in Figures 6 and 7. These PTL circuits are prepared using only n-type JNTs. Keeping the gate voltages fixed, if we invert the inputs, PTL AND gate can work as an NAND gate and OR gate can work as an NOR gate. Thus, evaluating PTL AND and OR gate performance of JNT we can predict performance in NAND and NOR too.