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Four-State Hybrid Spintronics–Straintronics for Ultra-Low Power Computing
Published in Krzysztof Iniewski, Tomasz Brozek, Krzysztof Iniewski, Micro- and Nanoelectronics, 2017
Noel D’Souza, Jayasimha Atulasimha, Supriyo Bandyopadhyay
As mentioned in the previous section, by introducing magnetocrystalline anisotropy in the magnetostrictive layer, the multiferroic nanomagnet can be made to possess four possible stable magnetization directions (up, right, down, left) in which four 2-bit combinations can be encoded (00, 01, 11, 10). Logic operations are carried out by implementing a clock that flips the nanomagnet’s magnetization orientation in response to one or more inputs to generate the desired output. By manipulating the dipole interactions between neighboring nanomagnets, various types of logic gates can be implemented. The four-state scheme with multiferroic nanomagnets possessing biaxial magnetocrystalline anisotropy can be exploited to realize four-state NOR logic [29] (NOR represents a universal logic gate in digital circuits since it, like NAND logic, can be used to create all other logic gates). This is accomplished by applying a clock cycle consisting of a sequence of stresses to the output nanomagnet with an input nanomagnet on each side of it. Therefore, the final state of the output magnet is determined by its dipole interactions with the input magnets, while the stress cycle and an applied dc bias magnetic field provide the conditions necessary for NOR logic.
Four-State Hybrid Spintronics–Straintronics
Published in Tomasz Wojcicki, Krzysztof Iniewski, VLSI: Circuits for Emerging Applications, 2017
Noel D’Souza, Jayasimha Atulasimha, Supriyo Bandyopadhyay
As mentioned in Section 4.5.1, by introducing magnetocrystalline anisotropy in the magnetostrictive layer, the multiferroic nanomagnet can be made to possess four possible stable magnetization directions (“up,” “right,” “down,” “left”) in which four 2-bit combinations can be encoded (“00,” “01,” “11,” “10”). Logic operations are carried out by implementing a clock that flips the nanomagnet’s magnetization orientation in response to one or more inputs to generate the desired output. By manipulating the dipole interactions between neighboring nanomagnets, various types of logic gates can be implemented. The four-state scheme with multiferroic nanomagnets possessing biaxial magnetocrystalline anisotropy can be exploited to realize four-state NOR logic (D’Souza, Atulasimha, and Bandyopadhyay 2011a) (NOR represents a universal logic gate in digital circuits as it, similar to NAND logic, can be used to create all other logic gates). This is accomplished by applying a clock cycle consisting of a sequence of stresses to the output nanomagnet with an input nanomagnet on each side of it. Therefore, the final state of the output magnet is determined by its dipole interactions with the input magnets, whereas the stress cycle and an applied DC bias magnetic field provide the conditions necessary for NOR logic.
Widget Deconstruction #2: USB Flash Drive
Published in John D. Cressler, Silicon Earth, 2017
nor flash and nand flash get their names from the structure of the logical interconnections between memory cells (if you need a refresher on digital logic, see Appendix B). In nor flash (Figure 6.20), memory cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of the cells resembles the parallel connection of transistors in a complementary metal oxide semiconductor (CMOS) nor logic gate (hence the name). In nand flash (Figure 6.21), however, cells are connected in series, resembling a CMOS nand logic gate, preventing cells from being read and programmed individually. That is, the cells are connected in series and must therefore be read in series.
120 Gb/s all-optical NAND logic gate using reflective semiconductor optical amplifiers
Published in Journal of Modern Optics, 2020
The NAND logic gate produces ‘1’ output only if any of its inputs are ‘0’; thus NAND gate is the invert of an AND gate. The NAND schematic diagram and its corresponding truth table using the dual-RSOAs-based scheme are shown in Figure 2.