China
Africa
Explore chapters and articles related to this topic
CMOS Manufacturability
Published in Krzysztof Iniewski, Circuits at the Nanoscale, 2018
Semiconductor technology is an art of building transistors. Throughout the last 50 years, it was driven by field-effect transistor (FET) development. It was FET gate CD, FET gate oxide thickness, and FET junction depths and profiles that had to be scaled down according to the Dennard rules [4] to make faster and cheaper devices. Accordingly, leading device manufacturers, product lines, and pure-play foundries have recently started implementing the 65 nm node and are looking forward to the 45 nm process. The underlying paradigm used to be that the shrink path would eventually provide enough transistors to capture any information in the digital form, be it originally analog or digital. This paradigm, despite all the years of following Moore’s law, proved to be correct only to some degree. There are still new applications and economic opportunities ahead for analog and radiofrequency (RF) devices within the existing process capabilities that have only been marginally comprehended.
Iodine that sustains electronic and information materials
Published in Tatsuo Kaiho, Iodine Made Simple, 2017
When processing the silicon semiconductor integrated circuit, the circuit pattern is transferred to the photoresist, and after exposure, the exposed areas are etched. Then, metal used as metal wiring is embedded in the groove created by the etching. With half the distance of the center distance of the adjacent metal wiring as standard, the expression 65 nm process is used in reference to silicon semiconductors. The standard leading edge is 65 nm process, but the next generation is said to be 45 nm process, indicating a high integration trend.
MOSFETs for RF Applications
Published in Frank Schwierz, Hei Wong, Juin J Liou, Nanometer CMOS, 2010
Frank Schwierz, Hei Wong, Juin J Liou
Figure 4.16 shows the maximum output power of 65-nm and 250-nm RF power MOSFETs having the optimum gate width (see Fig. 4.15 for the 65-nm devices) as a function of frequency. The higher output power of the 250-nm devices up to about 10 GHz results from the higher operating voltage of 2.5 V, compared to 1 V for the 65-nm devices. The 65-nm devices provide an improved power performance when the frequency is increased beyond 15 GHz.
Heavy-ion and pulsed laser induced single-event double transients in nanometer inverter chain
Published in Radiation Effects and Defects in Solids, 2023
Wen Zhao, Wei Chen, Chaohui He, Rongmei Chen, Fengqi Zhang, Xiaoqiang Guo, Chao Lu, Chen Shen
The test structure is implemented in a 65-nm bulk CMOS technology. It includes the target circuit where the single-event transients are generated and the measurement circuit. The SET measurement circuit is based on an on-chip self-triggered method, which is introduced in our previous work (14). The target circuit is an inverter chain arranged in a serpentine style, with 100 stages in a row and 10 rows in parallel, as shown in Figure 1. The PMOS/NMOS transistors in the same row share a common n-well/p-well. Nearby rows of the inverter chain are physically separated with 4.2 µm. This separation reduces the possibility of the charge sharing between nearby-row transistors. The gate length of all transistors in this chain is 60 nm. The gate widths of PMOS and NMOS transistors are 320 and 240 nm, respectively. The nominal supply voltage of the inverter chain is 1.2 V, and the chain input is biased at the ‘low’ state (0 V). The top package of the device was removed prior to the heavy-ion irradiation and pulsed laser irradiation.
A 585.9 µW Complementary VCO with an LC Head-and-Tail Filtering Achieving 196.7 dBc/Hz FoM
Published in IETE Journal of Research, 2023
Mikki How-Wen Loo, Harikrishnan Ramiah, Chee Cheow Lim
The proposed VCO is designed and simulated using 65-nm CMOS technology. The physical chip layout extraction of the proposed VCO is shown in Figure 6, occupying a core area of 0.195 mm2. The NMOS and PMOS –gm differential pairs are sized and , respectively. Three inductors are employed: an inductor for the main LC tank (LM = 1.436 nH; QM = 16.21), and another two inductors used for LC tail (LT = 0.932 nH; QT = 16.86), and head filters (LH = 0.974 nH; QH = 15.54). The main LC tank employs 4-bit MOM switchable capacitors with an LSB of 27.33 fF, together with a fixed MOM capacitor of 278.67 fF. As for CT (CH), similar 4-bit MOM switchable capacitors are employed, where LSB is 5.78 fF (2.13 fF) and a fixed capacitor is 110.46 fF (74.09 fF). Electromagnetic (EM) effects are taken into account by EM simulation of inductors and the metal traces to the –gm differential pair and the capacitor arrays. The EM effect was suppressed with proper insulation using guard rings. The main contributor is among the inductor on the main LC tank and tail filter, which only exhibits a coupling coefficient k of 0.027 and a mutual inductance of 0.033 nH.
Design and analysis of 73-106 GHz CMOS injection-locked frequency divider
Published in International Journal of Electronics, 2021
Yo-Sheng Lin, Kai-Siang Lan, Chih-Wei Wang
in which fL,in is the minimum locked input frequency of the frequency divider. Table 1 is a summary of the implemented 73–106 GHz CMOS ILFD on a cost-effective 90 nm CMOS process, and recently reported state-of-the-art CMOS and SiGe BiCMOS ILFDs with similar operation frequency (Chao & Luong, 2012; Chen, Li, Huang, Chuang et al., 2010; Choi et al., 2010; Fu et al., 2014; Gu et al., 2007; Hietanen et al., 2019; Kazuno et al., 2017; Kim et al., 2008; Tseng & Lin, 2018; Wan et al., 2019; Yamamoto & Fujishima, 2006; Yin & Luong, 2012; Zhang et al., 2017; Zhu & Zhao, 2020). As can be seen, our ILFD occupies small core area, consumes low power, shows large locking range, and achieves one of the best FOMs. The performance of the ILFD2 can be further enhanced if a more advanced CMOS process, such as the 65 nm CMOS process in Chao and Luong (2012), is available. The result indicates that the ILFD topology is suitable for W-band and even higher frequency band communication systems.