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Soft-Error Mitigation Approaches for High-Performance Processor Memories
Published in Tomasz Wojcicki, Krzysztof Iniewski, VLSI: Circuits for Emerging Applications, 2017
Radiation-hardened microprocessors for use in aerospace or other high-radiation environments [1] have historically lagged behind their commercial counterparts in performance. The RAD750 (BAE Systems Inc., Arlington, VA), released in 2001 on a 250-nm rad-hard process, can reach 133 MHz [2]. Recent updates of this device to a 150-nm process have improved on this, but only marginally [3]. This device, built on a radiation-hardened process, lags in part due to the difficulty in keeping such processes up to date, for relatively low-volume devices [4]. The SPARC AT697 (Atmel Corp., San Jose, CA) introduced in 2003 has an operating frequency of 66 MHz, uses triple modular redundancy (TMR) for logic, and error detection and correction (EDAC) and parity protection for memory, soft-error protection [5,6]. More recent radiation hardened by design (RHBD) processors have reached 125 MHz [7]. In contrast, unhardened embedded microprocessors contemporary to these designs achieve dramatically better performance on similar generation processes. For instance, the XScale microprocessor, fabricated on a 180-nm process, operates at clock frequencies over 733 MHz [8]. Ninety-nanometer versions of the XScale microprocessors achieved 1.2 GHz [9] with the cache performance being even higher [10]. More modern designs, such as those in 32-nm cell phone system on chip (SOC) devices, are multicore, out-of-order microprocessors, running at over 1.5 GHz [11]. As portable devices have become predominant, power dissipation has become the overriding concern in microprocessor design. The most effective means to achieving low power is clock gating, which limits circuit active power dissipation by disabling the clocks to sequential circuits such as memories. In caches and other memories, this means that the operation of clocking and timing circuits must also be protected from radiation-induced failures, including erroneously triggered operations.
Design and comparative analysis of memristor-based transistor-less combinational logic circuits
Published in International Journal of Electronics, 2022
Md Hasan Maruf, Md Shakib Ibne Ashrafi, A. S. M. Shihavuddin, Syed Iftekhar Ali
In 2014, Mehri et al. implemented an optimised memristor-based full adder where they used IMPLY logic for their design. They designed an 8-bit full adder where they used 27 memristors and presented 184 computational steps to design their full adder (Teimoory et al., 2014). In 2015, El-Slehdar et al. proposed a memristor-based redundant binary adder where they try to eliminate carry propagation using signed bit representation (El-Slehdar et al., 2015). In 2015, Singh presented a hybrid memristor-CMOS (MeMOS) based full adder where he used 180 nm process technology with 1.8 V operating voltage. In this paper, the author focused on four basic design parameters: delay, area, complexity and power. For delay, all the logic gates and full adder were in pico second (ps) range and for power, all were in micro watt (μW) range (T. Singh, 2015). In 2018, Karimi and Rezai proposed a new IMPLY logic where they proposed two new efficient architectures for their design: serial memristor-based full adder and parallel-serial memristor-based full adder (Karimi & Rezai, 2018). In 2019, Fouad and Redwan proposed a memristor-based quinary half adder where they modified the memristor-based ternary adder and redundant binary adder (Fouad & Radwan, 2019). Again in 2019, Khalid et al. proposed a full adder where they used MRL logic. They claimed better performance in delay, power consumption, and transistor count. They found total delay of 75.3ps in CMOS and 62.4ps in memristor-based full adder. Also, they calculated power consumption of 117.3uW in CMOS and 53.08uW in memristor-based adder (Khalid et al., 2019). This paper designs a full adder circuit using memristor where the basic logic gates are designed with MRL logic and no transistor has been used in the internal design.