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Power Electronic Converters
Published in Iqbal Husain, Electric and Hybrid Vehicles, 2021
The circuit topology of a buck-derived push-pull converter is shown in Figure 9.15. The circuit uses two switches on the input side and an inductor for energy storage on the output side. The center-tapped transformer is used for voltage scaling and electrical isolation. Switches S1 and S2 are turned on and off alternately with equal duty ratios within one switching period. The duty ratio for each switch can be varied between 0 and 0.5. A minimum dead time when both switches are off is guaranteed by the controller between the switching transition of the two devices to avoid the possibility of shoot-through across the supply voltage. The voltage gain of the push-pull converter is VoVin=2N2N1D,0<D<0.5
Inverters
Published in Timothy L. Skvarenina, The Power Electronics Handbook, 2018
Michael Giesselmann, Attila Karpati, István Nagy, Dariusz Czarkowski, Michael E. Ropp, Eric Walters, Oleg Wasynczuk
A circuit of the Class D voltage-source half-bridge series-resonant inverter (SRI) is presented in Fig. 5.60. It is composed of two bidirectional switches S1 and S2 and a series-resonant circuit L-C-R. Each switch consists of a transistor (power MOSFET, IGBT, or BJT) and an antiparallel diode. The switch can conduct either positive or negative current. It can only support, however, voltages higher than about -1 V. A positive or negative switch current can flow through the transistor if the transistor is ON. If the transistor is OFF, the switch can conduct only a negative current, which flows through the diode. The transistors are driven by nonoverlapping gating signals with a small dead time at the operating frequency f = 1/T. Switches S1 and S2 are alternately ON and OFF with a duty ratio of 50% or slightly less. The dead time is the time interval when both controllable devices are off. Resistance R is an AC load. If the inverter is a part of a DC-DC resonant converter, R represents an input resistance of a rectifier.
Power Converters Used in Body Systems
Published in Dorin O. Neacşu, Automotive Power Systems, 2020
Details of this waveform can be understood from analysis of the possible operation states. Each inverter branch has two possible states when we neglect the effect of the dead-time. Dead-time is the interval introduced in between the turn-off of a power MOSFET and the turn-on of the other MOSFET on the same inverter branch. It is used to prevent a short-circuit of the dc bus through two commutating transistors due to the inherent switching delays, which is detailed at the end of this chapter.
A New Switched Capacitor Based Multi-Level Inverter with Fewer Capacitors
Published in International Journal of Electronics, 2023
Ashutosh Kumar Singh, Rajib Kumar Mandal
In this article, PD-PWM is used to generate the gate pulse as the proposed topology has less total harmonic distortion (THD) and due to simplicity of PD-PWM. In Figure 5, PD-PWM technique is shown which is used for the proposed topology. It contains 16 carrier waves of triangular shape namely Cp1 to Cp8 for positive cycle and Cn1 to Cn8 for negative cycle, each having same frequency (fc) and same amplitude (Ac) and placed one above another as shown in Figure 5(a), and a hardware result of switching pulse for each switch is also shown in it. These carrier signals are compared with a reference sinusoidal signal having amplitude equal to the desired output amplitude (Aref) and frequency equal to the required output frequency. Logical comparison circuit is shown in Figure 5(b) and output of this circuit is denoted by P1 to P18. These outputs are further fed into other logic circuit, shown in Figure 5(c), to produce gate signal for switches. As some of the switches are complementary to each other, a dead time must be established for preventing any damage to supply and other components. As modulation index depends on the amplitudes of carrier and reference signal, therefore it can be calculated as equation (8), and its value will be in between 0 and 1.
Bi-directional DC/DC Converters Used in Interfacing ESSs for RESs and EVs: A Review
Published in IETE Technical Review, 2023
Om Prakash Jaga, Ritesh Gupta, Balaram Jena, Sumit GhatakChoudhuri
A three-phase DAB DC/DC converter consisting of twelve active switches, S1–S12, two capacitors, CB and CDC, three inductors, L1–L3 and three high-frequency isolation transformers, as shown in Figure 8(b) [38]. Dead-time significantly affects the converter performance for high switching frequency, wide voltage conversion and power ranges applications. In [38], dead-time effects are analysed in terms of voltage conversion ratio and phase shift on a three-phase DAB converter under different operating conditions. The main advantage of such a topology is that all active devices achieved ZVS during turn-on, which improves the converter's efficiency. A three-phase DAB is more efficient and requires around one-third of the capacitances on LV and HV sides than a single-phase DAB. Such a topology is suitable for RESs, interfaced with BESS, EVs, UPSs, etc.
Dead-time optimisation with reducing voltage distortion for nine-switch inverter
Published in International Journal of Electronics, 2018
Mohamadreza Alizadeh Pahlavani, Meisam Sanatgar Hasankiadeh, Aref Bali Lashak
In conventional two-level inverters, converter needs to be protected against short circuit, and this is usually done by injection of dead-time in the switching pulses of the switches placed in the same leg. Dead-time triggers a slight turn-ON delay in switches and thus prevents switches from turning-ON at the same time and thereby protects the circuit from damage (Gao et al., 2010; Liu et al., 2009a). In nine-switch inverters, injection of the dead-time to switching pulses of upper switch and lower switch before logical XOR is a common way of protecting circuit against simultaneous turn ON of three existing switches in each leg (Gao et al., 2010; Liu et al., 2009a). Injection of dead-time to switching pulses changes the voltage waveform that the resultant voltage error (the difference between output voltages before and after dead-time injection) is in form of rectangular pulses. For example, the waveform of the voltage error after dead-time injection with respect to output current is shown in Figure 3. According to Figure 3, area of each pulse and the number of pulses are, respectively, and , where is DC voltage source, is dead-time, is carrier period and is period of reference signals.