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Data Converter Basics
Published in Bang-Sup Song, Micro CMOS Design, 2017
In practice, the ADC performance is limited not only by the quantization noise but also by many other nonideal factors such as noises from other circuit components, power supply coupling, noisy substrate, timing jitter, settling, and nonlinearity. Therefore, SNR is always lower than DR, because the ADC noise floor can be elevated with a large signal present. An alternative definition of resolution is the effective number of bits (ENOB), which is derived from the definition of SNDR.
Data Converters
Published in Nihal Kularatna, Electronic Circuit Design, 2017
If we choose a much higher sampling rate (K × fs), as in Figure 5.33a, the quantization noise is distributed over a wider bandwidth, as shown in Figure 5.33b. If we then apply a digital low-pass filter to the output, we remove much of the quantization noise but do not affect the wanted signal, so the ENOB is improved. We have performed a high-resolution A/D conversion with a low-resolution ADC.
Optical Coherent Detection and Processing Systems
Published in Le Nguyen Binh, Digital Processing, 2017
The ENOB of an ADC is the number of bits that an analog signal can convert to its digital equivalent multiplied by the number of levels represented by the module-2 levels, which are reduced due to noises contributed by electronic components in such convertor. Thus, only an effective number of equivalent bits can be accounted for. Hence, the term ENOB is proposed.
A full input range, 1–1.8 V voltage supply scalable analog voltage comparator in 180nm CMOS
Published in International Journal of Electronics, 2021
Ashima Gupta, Anil Singh, Alpana Agarwal
To show its application, the proposed comparator is used in the 4-bit flash ADC and further extended to 5-bit. Figure 8 shows the simulated Differential-Nonlinearity (DNL) and Integral-Nonlinearity (INL) of the converters. The calculated INL is ± 0.4 LSB and DNL is ± 0.4 LSB for 4-bit flash ADC. For 5-bit flash ADC, the measured INL is ±0.6 LSB and DNL are ±0.42 LSB, respectively. Figure 9 shows the transient analysis of 4-bit flash ADC where a slow triangular signal is provided at the input to obtain the digital output (M3-M0). To show the dynamic performance, the Fast Fourier Transform (FFT) of 4-bit flash ADC is depicted in Figure 10 at the input frequency of 24.21 MHz and sampling frequency of 400 MHz. The calculated value of Spurious-Free Dynamic Range (SFDR), Signal-to-Noise and Distortion Ratio (SNDR), Effective Number of Bits (ENOB), and Signal-to-Noise Ratio (SNR) are 31.7 dB, 22.99 dB, 3.52, and 24.06 dB, respectively. Figure 11 depicts the total power consumed by the 4-bit flash ADC is 3.72 mW.
Time Resolution of a Cs2LiYCl6:Ce3+ Detector Measured with a DRS4 Waveform Digitizer
Published in Nuclear Technology, 2019
The data acquisition system used was the DRS4 waveform digitizer developed at Paul Scherrer Institute (PSI) in Switzerland. The core part of this digitizer is the DRS4 chip. The chip is able to acquire input signals with a sampling rate adjustable between 0.7 and 5.12 giga samples per second (GSPS). The sampling rate selected in this work was 5.12 GSPS because more accurate time information can be extracted when the pulses are digitized at higher sampling rates. The number of sampling points in each acquired waveform was 1024. This corresponds to a waveform acquisition window of 200 ns. The acquisition time window is adequate to cover the rising edge of typical scintillation pulses on which the extraction of time information relies. The digitizer’s effective number of bits is 11 and was measured by sampling the spectrally pure sinusoidal signal and then calculating the root mean square and noise level recorded by the digitizer.11 It is not as high as those of flash analog-to-digital converter–based digitizers (i.e., 11 versus 14 to 16 bits). The lower bit resolution is one of the drawbacks of the DRS4 waveform digitizer for this specific application. Nevertheless, it was shown to be high enough to obtain accurate time information when using high sampling rates [i.e., a few picoseconds (ps) at 5.12 GSPS]. Prior to performing any measurements, the digitizer was calibrated using the amplitude and time calibration algorithms implemented in the digitizer control software designed by PSI as well. For the voltage calibration, a digital-to-analog converter inside the digitizer was used to generate the calibration signal. An internal 100-MHz clock was employed to determine the effective width of each cell for the timing calibration.12 In the detector time resolution measurements, the digitizer was internally triggered at the pulse rising edge with a threshold of 15 mV. The digitized data were transferred to a host computer and saved in text files for off-line processing with Matlab.
Monitoring soil water content and its salinity with high-precision and low-cost in-situ sensors
Published in European Journal of Environmental and Civil Engineering, 2023
Xavier Chavanne, Jean-Pierre Frangi
The core technology of the measuring circuit is a self-balanced Wheatstone bridge, of which a simplified diagram is shown Figure 2. The entire circuitry is analog. It determines at a frequency the admittance at its input through two direct voltages, each proportional to one admittance part, conductance or capacitance The situation corresponds to an on-board admittance with resistance and infinity capacitance in series. Bridge contains two branches, similar on their structure, each dedicated to one part of An excitation voltage from a quartz-tuned oscillator, is applied between admittance ends. The resulting current is balanced owing to a feedback loop made of a current/voltage converter, and a de-modulator and an integrator in each branch. Feedback input is the unbalanced signal at Integrator output are the feedback DC voltage VC and VG which build up until the bridge is balanced and signal sent to demodulators becomes zero The loop thus provides proportional to each part of the current to be balanced, and, as a result, to Voltages are fed to modulators to construct the alternating current which offsets Voltages are limited by component supply and linearity conditions to a range from −3.5 to 3.5 V. They are digitised by an Analog-to-Digital Converter (A/DC) in the digital circuit. Data reported in the whole article, except in Figure 3, correspond to the digitalised output. In the case of last generation sensors voltages are digitised by a bipolar 24-bit A/DC (MCP3903-I/SS of Microchip Technology Inc.), after a voltage division by 7 to accommodate ADC full scale of 1 V. Considering 22 as the effective number of bits the theoretical resolution would be few μV. Actually, due to bridge noise, we observe a resolution of 0.2 mV from repeatability of measurements at same bridge input. For one measurement the A/D converter performs a sampling to reduce the noise (typ. 50 samples).