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The Voltage-Amplifier Stage
Published in Douglas Self, Audio Power Amplifier Design, 2013
Despite the very simple resistive load the VAS generates a fairly low level of distortion. This is because at LF, global feedback linearises the whole amplifier, while at HF the VAS is linearised by local NFB through Cdom, with a smooth transition between the two. It is therefore important that the local open-loop gain of the VAS (that existing inside the local feedback loop closed by Cdom) be high, so that the VAS can be well linearised. In Figure 7.1a, increasing the value of Rc in an attempt to increase the gain will decrease the collector current of the VAS transistor, reducing its transconductance and getting you back where you started; the gain will be low. An active load is very desirable to increase the effective collector impedance of the VAS and thus increase the raw voltage gain; either bootstrapping or a current-source works, but the current source is more dependable, and almost the universal choice for hi-fi or professional amplifiers.
Circuits and Circuit Laws
Published in Richard Cadena, Electricity for the Entertainment Electrician & Technician, 2021
An active load has active electronics that ensure the load receives the right amount of power. If the voltage applied to an active load drops, the current will rise so that the power stays the same. If the applied voltage rises, then the current will fall to compensate. If you are on portable generator power, you will often have the option of boosting the voltage using the automatic voltage regulator (AVR). However, boosting the voltage at a portable generator by adjusting the AVR makes the generator run harder and hotter, and can shorten its life. It will also increase the voltage to other loads closer to the supply, which may or may not be a problem.
Investigation of Adiabatic Logic in Nano-meter Technology
Published in International Journal of Electronics, 2023
Tarun Kumar Gupta, Shipra Upadhyay, Amit Kumar Pandey
A basic structure of proposed technique is shown in Figure 9. The proposed technique (MPFAL) is the modification of the PFAL adiabatic technique. The structure of proposed circuit (MPFAL) is similar to existing PFAL adiabatic technique. In the proposed design, cross-coupled inverters are used to latch the output, and functional blocks based on NMOS are put in the pull-up part that is in parallel with the PMOS transistors. The pull-up network will act as a transmission gate. When current is drawn from the power source during evaluation time, the technique’s effective resistance will decrease. In the pull-down network, one more power clock (PCLK2) is connected to gate of PMOS transistor M5. The transistor M6, which acts as a diode, behaves as an active load, and this is helpful in reducing losses. This diode provides a high impedance value in the discharging path. As a result, the output node discharges slowly at node capacitance. A PMOS transistor and a power clock for gating the PMOS are also used. The amplitude of power clock (PCLK2) is inverted, and it has double the frequency as compared to the original power clock (PCLK). The extra transistors M5 and M6, which are added in the proposed technique, help reduce the switching ON time. Transistor M5 turns ON as a result, assisting in shortening the discharging time and enabling the technique to use less power. The operation of proposed technique is explained in four clock phases.
Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator
Published in IETE Journal of Research, 2023
Abhay S. Vidhyadharan, Gangavarapu Anuhya, Shivangi Shukla, Sanjay Vidhyadharan
The schematic of the conventional voltage comparator [19] is shown in Figure 1. The comparator comprises of a cascade of voltage-to-current and current-to-voltage converters. NMOSFETs MN1 and MN2 are the input transistors of the first stage differential amplifier, while PMOSFETs MP1 and MP2 act as active loads that convert the differential input voltage into proportional branch currents. NMOSFET MN3 is used to set the biasing tail current. The second stage, made up of MN4 and MP3, acts as a common source amplifier with MN4 as a fixed-bias load. This comparator with current-mirror active-load has three significant advantages, viz. high output-resistance, tiny die area, and easy conversion of differential input to single-ended output.
Analysing a common-source amplifier implemented with floating-gate transistors and coupled feedback loop
Published in International Journal of Electronics, 2022
A. S. Medina Vázquez, M. E. Meda Campaña, S. A. Rios Salcedo, F. J. Plasencia Jauregui
In Figure 1(a), the transconductor element is a MIFGMOS transistor M1a in common-source amplifier configuration (CSAFG) with an active load in diode-connection configurations (M2a transistor) with direct feedback through one of its control gates, which is connected in a mirror configuration to a M3a transistor, as it would be in a conventional differential amplifier. In counterpart, in part (b) of the figure, we have the MOS version (CSAMOS). Both versions are compared in this document. As is known, the active load (M2a and M2b) can be simplified as a resistor for small-signal analysis ‘(Razavi, 2017)’.