Explore chapters and articles related to this topic
From Editor-in-Chief's Desk
Published in IETE Journal of Education, 2019
P V Ananda Mohan
In the paper “From design to tape-out in SCL 180nm CMOS Integrated Circuit Fabrication Technology” Joydeep Basu deals in detail with the complete steps involved from design to tape out of CMOS VLSI chips in the foundry at SCL, Chandigarh, India. We believe it to be informative to the students and designers especially of Analog VLSI chips who want to get their designs fabricated to assess the performance.