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Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Nishath Verghese, Makoto Nagata
The primary mixed-signal noise coupling problem from fast-changing digital signals, coupling to sensitive analog nodes, is shown schematically in Figure 23.1. Another significant cause of undesired signal coupling is the cross talk between analog nodes themselves owing to the high-frequency/high-power analog signals. One of the media through which mixed-signal noise coupling occurs is the substrate. Digital operations cause fluctuations in the underlying substrate voltage, which spreads through the common substrate causing variations in the substrate potential of sensitive devices in the analog section. Similarly, in the case of cross talk between analog nodes, a signal can couple from one node to another via the substrate. This phenomenon is referred to as “substrate coupling” or “substrate noise coupling”.
Electro-Thermal Considerations Dedicated to 3D Integration; Noise Coupling
Published in Thomas Noulis, Noise Coupling in System-on-Chip, 2018
Yue Ma, Olivier Valorge, J. R. Cárdenas-Valdez, J. C. Núñez-Perez, J. Verdier, Francis Calmon, Christian Gontrand
Mixed Signal IC's design has become a key for systems-on-chip VLSIs. Functional analog blocks like VCOs, LNA, filters, and AD/DA converters are placed on a die with high speed digital processing elements composed of a few millions digital gates. Parasitic phenomenon, commonly called crosstalk, occurs between the noisy digital and the sensitive analog part of the device. Due to many parasitic coupling mechanisms, there is a distinct possibility that the transient regimes in the digital circuitry of this kind of device will corrupt low-level analog signals and seriously compromise the achievable performance [1]. One of the main coupling phenomenon is the substrate coupling. The chip substrate acts as a collector, integrator, and distributor of coupled noise on chip. Many developments describe methods to simulate this perturbing kind of noise [2–4]. However, the majority of the models presented only considers the package bonding; whereas, many different parts of the supply lines are important in substrate noise generation: PCB, package, pad ring, on chip metal lines, and other parasitic elements of supply lines.
Inductance Effects in Global Nets
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
In terms of substrate coupling, inductance effects increase this type of noise significantly. Overshoots and undershoots owing to inductance cause noise coupling through the common substrate, which is both difficult to measure and difficult to control. Substrate noise-conduction modes can be classified into (1) resistive coupling, (2) capacitive coupling, (3) impact ionization, and (4) body effect (Figure 41.7). All these modes involve currents running into the substrate from the drains or the sources of transistors and affecting other devices. Ideally, the p-bulk is grounded, which always reverse biases the p – n junctions at the drains and sources of NMOS transistors assuming that ground is the lowest voltage that can appear at the drain or source of any transistor. Similarly, the n-well is connected to VDD to reverse bias the drains and sources of PMOS transistors. However, inductance effects cause overshoots and undershoots that can forward bias these junctions resulting in currents flowing into the substrate causing substrate coupling. For that reason, substrate coupling noise is sometimes called bootstrap noise. Also, if the bulk is biased with a switching ground bus, the ground on the bulk is not perfect because switching transients will cause voltage drops across the line. Hence, the switching transients on the power supply line can couple to transistors resistively through the p+ bulk contacts. The parallel summation of bulk contacts and epitaxy resistances provides a very low impedance path (nearly short) to the p+ buried layer.
20 GHz Substrate Crosstalk Sensor for Mobile Communication Applications
Published in International Journal of Electronics Letters, 2022
K. Moustakas, T. Noulis, S. Siskos
Various modelling techniques and simulation flows have been proposed to estimate the noise propagation and impact on the design phase. To validate the accuracy and reliability of the substrate coupling aware design flow, direct measurement of the substrate noise signal and comparison to the simulation results is required. Additionally, identification of the sensitive substrate coupling paths can be achieved only by direct measurements during the SoC operation.