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System-Level Design and Simulation of Nanomemories and Nanoprocessors
Published in Sergey Edward Lyshevski, Nano and Molecular Electronics Handbook, 2018
Shamik Das, Carl A. Picconatto, Garrett S. Rose, Matthew M. Ziegler, James C. Ellenbogen
Thus, to develop and simulate efficiently models for molecular-scale devices, we utilized the commercial Cadence Spectre simulator. This software permits the description of the empirical behavior of devices using the analog hardware description language (analog HDL) Verilog-A. This modeling approach is similar to one described elsewhere [94–96], except that the empirical equations derived in this work were tailored to the devices employed in the Lieber–DeHon nanomemory system. These empirical equations were incorporated into the Spectre circuit simulator, which supports co-simulation of both Verilog-A components and conventional SPICE-level devices.
A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime
Published in Australian Journal of Electrical and Electronics Engineering, 2021
A CMOS NAND3 gate comprises three NMOS devices in PDN and three PMOS devices in PUN for the three primary inputs. In CMOS NAND3 gate, NMOS devices are connected in series while PMOS devices are connected in parallel as shown in Figure 25. NAND3 gate for the different leakage reduction techniques are designed by following the basic schematic ideas of the techniques as discussed in the section 4 as well as the logical diagram of the CMOS NAND3 gate as shown in Figure 25. The comparison among the methods is concluded for low power (LP) Berkeley Short-channel IGFET Model4 (BSIM4)Predictive Technology Model (PTM)16 nm technology node using Cadence’s tools.The considered channel length for the MOSFET devices is 16 nm. The channel widths of the devices are arranged as per the channel length and these are 2× for the NMOS and 4× for the PMOS devices.The Nominal values for the power supply and the effective oxide thickness are 0.9 V and 1.2 nm respectively at 16 nm technology node. The room temperature is fixed for all the methods. For making a fair comparison among the methods, the identical parameters are assumed if needed for all the methods. The input SPICE netlists are prepared for all the methods and simulated by using Spectre circuit simulator. Leakage power dissipation (PD) and propagation delay are the key parameters specially in nanoscale regime (Kajal and Sharma 2021). Therefore, both the parameters are estimated for all the methods. The balance between them is managed by PDP. So, PDP is also calculated for all the methods. The reliability comparison is done for the PDP parameter. The simulation results for the different leakage reduction techniques are presented in Table 2.