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FDSOI RF Flexible Electronics
Published in Chinmay K. Maiti, Fabless Semiconductor Manufacturing, 2023
Moreover, the planar FDSOI devices have very similar architecture and fabrication process as their silicon bulk predecessor MOSFET and therefore it simplifies, for instance, the adaptation of the existing device simulation tools. SOI technology is a technology based on wafers composed of a layer of monocrystalline silicon on an insulating film, usually silicon dioxide, the substrate also being in monocrystalline silicon (Figure 7.5(a)) [79]. Of many manufacturing processes exist such as epitaxial growth of silicon on an insulating layer [80,81], the recrystallization of a thin layer of silicon using a laser [82], the separation of silicon via the implantation of oxygen [83,84], or the transfer of a substrate of silicon on another via a bonding [85–88]. From these various strategies, three manufacturing methods have been developed for several decades to produce SOI substrates: SIMOX (separation by implantation of oxygen) [83, 84, 87], BESOI (bonded and etch-back SOI) [85,86], and SmartCut [87,88]. The first method is based on the formation of a buried oxide layer, while the two others are based on the bonding of silicon substrates. Starting with two bulk silicon wafers A and B, a thermal oxide is first grown of wafer A, followed by the implantation of hydrogen at a chosen depth below the surface of wafer A to create a weakened layer. The two wafers are then bonded together, encapsulating the oxide layer between two silicon layers, wafer A is then separated from wafer B at the weakened layer. Wafer B finally undergoes thermal annealing and polishing, resulting in an SOI wafer, whereas wafer A can be reused.
SOI Technologies for RF and Millimeter-Wave Applications
Published in Simon Deleonibus, Convergence of More Moore, More Than Moore, and Beyond Moore, 2021
Martin Rack, Jean-Pierre Raskin
Two main flavors of SOI devices exist: (i) PD-SOI and (ii) FD-SOI for the most advanced nodes. PD-SOI is characterized by an active silicon film typically thicker than 50 nm, while FD-SOI has an active silicon thickness roughly below 10 nm. In a PD-SOI MOSFET, the vertical space charge region induced by an applied gate voltage does not extend over the entire thickness of the active silicon layer, and a volume of unmodulated silicon (body) remains below the device’s channel. In an FD-SOI, however, the film is so thin that the entirety of the active silicon layer is modulated by the gate voltage.
Nanoscale MOSFETs and Similar Devices
Published in Vinod Kumar Khanna, Introductory Nanoelectronics, 2020
Introspection of the short-channel effects reveals that they weaken the controlling ability of the gate over the channel and create undesirable leakage currents that seriously impair the functioning of the MOSFET by making it difficult to deplete the channel for current cessation. Therefore, the elimination of these effects required a technological innovation. A major technological breakthrough involved the use of silicon-on-insulator (SOI) wafers as the starting manufacturing material for MOSFETs in place of the bulk silicon wafers used for fabricating the traditional planar MOSFETs. The SOI wafers have a trilayer structure consisting of a bottom thick silicon handle layer, a buried oxide layer, and a thin top silicon active device layer. The SOI wafer is made by wafer bonding or separation-by-implantation of oxygen (SIMOX) techniques.
Simulation-based analysis of an L-patterned negative-capacitance dual tunnel VTFET
Published in International Journal of Electronics, 2023
Girdhar Gopal, Harshit Agrawal, Heerak Garg, Tarun Varma
The simulation approach employed in this work is also valid for p-channel NCFET (Saha, 2021; Zhou et al., 2016). The tunnelling probability of TFET depends on energy band gap, so band gap narrowing is adopted in simulator. A doping dependent mobility model is considered in simulator. Using TCAD simulation, the effect of varying ferroelectric parameters such as TFE on the gate-capacitance, parasitic capacitances, and drain-current characteristics of the NCTFET has been observed. The device’s process flow can be as follows: After masking the oxidised silicon wafer, photo-lithography can be utilised to etch and pattern the DTD. Masked silicon (p++ doped) can be placed in the patterned area. In the intrinsic layer, the process can be repeated. Regular SOI substrates are made by silicon oxidation and etching out the undesirable oxide later.
Sensitivity of SET Pulse-Width and Propagation to Radiation Track Parameters in CMOS Inverter Chain
Published in IETE Journal of Research, 2022
SOI technology is a promising candidate for radiation-prone applications due to its buried oxide and smaller silicon thickness and hence preferred over bulk counterpart. The comparative study of SET propagation in SOI and bulk inverter chain is reported for higher technology nodes [9–14]. However, the comparison of SET pulse-width and propagation in sub-50 nm bulk-and SOI-based inverter chain and their sensitivity to radiation parameters are not yet reported, to the best of our knowledge. In this paper, a comprehensive analysis of heavy-ion induced SET in CMOS inverter and inverter chain is carried out for both bulk and SOI at 45 nm technology node. The ion strike is simulated in the OFF state NMOS of the CMOS inverter. The modification of SET pulse width after propagating through the chain of inverters is analysed. The sensitivity of the propagated SET pulse width on main radiation parameters such as LET, track length, angle of incidence, characteristic radius, and time of the track is studied through three-dimensional (3-D) TCAD simulations.
Design and Optimization of a Dual-Source Triple Gate FET Using Electrostatically Induced Reconfigurable Property
Published in IETE Technical Review, 2022
Antara Kundu, Priyanka Saha, Subir Kumar Sarkar
SOI technology is implemented here to isolate silicon channels from the substrate, thereby reducing the parasitic capacitances and associated losses. The work functions of gate metals of PG1, PG2, and CG are specified by ΦG1, ΦG2, and ΦG3, respectively, while the channel forms Schottky junctions (SJs) with metallic nickel silicide (NiS2) source (S) and drain (D) regions. The silicon channel is doped uniformly with p-type dopants (1016/cm3). The gate oxide thickness is denoted by tox. The dimensions of all the device parameters used during simulation are enlisted in Table 1.