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Modal Field of Power–Ground Planes and Grids
Published in Xing-Chang Wei, Modeling and Design of Electromagnetic Compatibility for High-Speed Printed Circuit Boards and Packaging, 2017
The rapid growth and convergence of digital computing and wireless communication have been driving the semiconductor industry to integrate more and more circuits on PCBs and into one single package. At the same time, the voltage supply level is continuously reduced with the ever-increasing working frequency. These make the electromagnetic compatibility (EMC), including the signal integrity and power integrity, a very critical issue for the successful design of PGPs and PGGs [3]. Considering the harmonics of the increased clock frequency, the noise spectrum on PCBs and inside the package will cover very high frequency. With this ever-decreasing wavelength, the electromagnetic wave fluctuation inside PGPs and PGGs cannot be ignored. This requires us to use the electromagnetic and microwave theory in all aspects of future circuit system, including modeling, design, and testing. We need to study the modal behaviors of the electric and magnetic fields, instead of the voltage and current for high-speed, high-power, and high-density electric circuit.
Power and Signal Integrity Challenges in 3D Systems-on-Chip
Published in Aida Todri-Sanial, Chuan Seng Tan, Krzysztof Iniewski, Physical Design for 3D Integrated Circuits, 2017
3D-ICs are expected to be heavily power-gated due to the importance of subthreshold leakage current in nanoscale bulk CMOS technologies. Furthermore, with heterogeneous integration, the switching activity factor of different blocks/planes is expected to significantly vary, emphasizing the need for power gating. Power gating, however, significantly affects the system-wide power integrity of a 3D-IC, particularly in the presence of decoupling capacitors [52,53]. Various decoupling capacitor topologies are discussed in Section 6.3.2 to enhance power integrity in the power-gated 3D-ICs. Advantages of a reconfigurable decoupling capacitor topology are emphasized [54].
An Algorithm for Power Supply Noise Reduction Inserting Decoupling Capacitor in 2D and 3D IC Power Delivery Networks
Published in IETE Journal of Research, 2022
In the high-speed digital system era, one of the most important areas is the design and analysis of a power delivery network. The objective of a power delivery network is to provide clean power to core logic and I/O circuits in any digital system. With the scaling of IC feature size, the power and ground network distribution has become a challenging task [1]. With technology scaling, on-chip power distribution networks’ requirements are increased significantly. The transistor density becomes larger due to scaling. This huge amount of transistor produces faster and large current transients in the power delivery network with a higher switching speed [2]. An efficient power delivery network (PDN) is needed to resolve a high level of digital system signal integrity. Improper design of PDN can be a major cause of noises, such as IR-drop, ground bounce and electromagnetic inference [3]. It is very important to maintain the power integrity for the performance of an IC. Compromising this may cause logic errors and slow transition. As the ICs operate at high frequencies and consume a large amount of power, it leads to large current flows in the PDN, which causes large IR drop and Ldi/dt noise [4]. High frequencies can cause inductive effects and this leads to trigger resonance, which presents a large impedance in PDN. Several I/Os cause serious simultaneous switching noise (SSN) in the PDN. All of these may result in power rail collapse and affect the operation of circuits [4]. The performance and reliability of the IC will be severely compromised if the drops in supply voltages become higher. Besides this, excessive overshoot of the supply voltage can affect the circuit functionality [5].