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Low-Power Techniques for Network-on-Chip
Published in Santanu Kundu, Santanu Chattopadhyay, Network-on-Chip, 2018
Santanu Kundu, Santanu Chattopadhyay
The principle of power gating is to selectively powering down certain blocks in the chips while keeping other blocks powered up. The goal of power gating is to minimize leakage current by temporarily switching some blocks to the power-down mode that are not required to be in the active mode while minimizing the impact on performance. Power gating is more persistent than clock gating that it affects interblock interface communication and adds significant time delays to safely enter and exit the power-down mode. Power gating to some portions of the design can be controlled by software as a part of device drivers or initiated in hardware by timers or system-level power management controllers. Architectural trade-offs in any power-gated design are as follows: The amount of possible leakage power savingsThe energy dissipated during entering and leaving such leakage saving modesFrequency of entering into the power gating and active modesPerformance penalty during entry and exit times
Placement-Driven Synthesis Design Closure Tool
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
Charles J. Alpert, Nathaniel Hieter, Arjen Mets, Ruchir Puri, Lakshmi Reddy, Haoxing Ren, Louise Trevillyan
In general, power gating can be physically implemented in the designs using block-based coarsegrained power gating and intrablock fine power gating (similar to multiple-supply voltages). In a block-based implementation, the footer (or header) switches surround the boundary of the block, as shown in Figure 39.14. This physical implementation is easier because it does not disturb the internal layout of the block. However, it has a potential drawback in terms of larger IR drop on the virtual ground supply. For IP blocks, this is the preferred implementation technique for power gating. Fine-grained power gating, as shown in Figure 39.15, where the footer switches are implemented within the logic in a regular layout are more desirable in a high-performance design where the voltage drop across the power gate as well as IR and EM (electromigration) requirements are more stringent.
Digital IC Design for Transceiver SOC
Published in Kaixue Ma, Kiat Seng Yeo, Low-Power Wireless Communication Circuits and Systems, 2018
Wang Yisheng, Kaixue Ma, Kiat Seng Yeo
The two major technologies in the low-power design methodology to save power are multiple-voltage and power gating technology. The detailed discussion on the two technologies will be covered in the low-power methodology section of this chapter (Section 14.5). For the power gating technology, the power switcher cell is used to turn on or turn off a specific module, and isolation cells are used to isolate the signal between the power-gated block and always on domain, and the state retain cells are used to keep the state when power is off. For multiple supply voltages, level shifters are needed to transfer the signal level between different voltage domains.
Hybrid buffers based coarse-grained power gated network on chip router microarchitecture
Published in International Journal of Electronics, 2020
Yogendra Gupta, Lava Bhargava, Ashish Sharma, M.S. Gaur
As shown in Figure 7(a) power-gating technique is implemented by putting high threshold voltage header transistors between the supply voltage and the power gated block. Therefore, the whole router block could be turned ON and OFF by controlling the sleep signal. Power-gating technique cut-off the supply voltage thus avoiding static power consumption. In NoC power-gating idle routers are entirely shut down and then wake up them when new packets arrive. However, applying power to NoC routers has some limitations such as energy overhead and latency overhead.