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Data Conversion
Published in Mike Tooley, Aircraft Digital Electronic and Computer Systems, 2023
The priority encoder is a logic device that produces a binary output code that indicates the value of the most significant logic 1 received on one of its inputs. In this case, the output of IC2 will be the most significant logic 1 and hence the binary output code generated will be 010, as shown in Figure 3.9b. Flash ADC are extremely fast in operation (hence the name), but they become rather impractical as the resolution increases. For example, an 8-bit flash ADC would require 256 operational amplifier comparators and a 10-bit device would need a staggering 1,024 comparator stages! Typical conversion times for a flash ADC lie in the range 50 ns to 1 μs, so this type of ADC is ideal for ‘fast’ or rapidly changing analogue signals. Due to their complexity, flash ADC are relatively expensive.
Analog Circuit Design
Published in Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik, Introduction to Microelectronics to Nanoelectronics, 2020
Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik
The flash converter consists of a resistor string to create 2n−1 reference levels and high-speed latched comparators to simultaneously compare Vin against each level, as shown in Figure 5.22. To handle analog signals, two resistors, 1.5R and 0.5R, are required. The comparators whose reference value is below Vin will produce the output as logic 1, and the remaining ones as logic 0. The resultant code is referred as the thermometer code and is converted to the desired output code using a priority encoder. Input sampling and latching takes place in the first phase of the clock period and decoding occurs during the second phase of the clock period. As entire conversion takes only one clock cycle, this ADC is the fastest one. Flash ADC is used for high-speed applications such as video processing and radar communications wherein the conversion rates are higher [3, 4].
High-Speed, Low-Power CMOS A/D Converter for Software Radio
Published in Krzysztof Iniewski, Circuits at the Nanoscale, 2018
James W. Haslett, Abdel-Fattah S. Yousif
The flash ADC architecture, in its simplest form, is a single cycle, high-speed converter where the input signal is compared to all the quantization levels of the ADC. An n-bit flash ADC requires 2n – 1 comparators to complete the comparisons and generate the thermometer code, which is later decoded into the output ADC bits. Figure 13.4 shows a diagram of a flash ADC converter, where the different reference voltages corresponding to the quantization levels are generated using a resistor ladder. The performance of the flash ADC architecture at GHz sampling rates is limited by two sources: device mismatches, which result in offset voltages at the comparator inputs, and the large silicon area needed to build the ADC, which also results in high-power consumption. At low resolution (6 bit or less) and sampling rate below 1.5 GHz, these issues can be resolved using a number of design techniques that are now commonly used.
A new 8-fold CMOS current-mode sawtooth folding amplifier
Published in International Journal of Electronics Letters, 2018
Munir A. Al-Absi, Muhammad Taher Abuelma’atti, Mohanad Elhassan, Sagar Dhar
Analogue-to-digital converters (ADC) are basic building blocks in modern mixed-mode analogue and digital signal processing. This justifies the quest for designing low-voltage, low-power, high-speed and compact ADCs. Over the years different architectures of ADCs have been developed. Among the available ADC designs it is well known that the full-flash ADC is the fastest. Unfortunately, an N-bits full-flash ADC requires 2N − 1 comparators and 2N equal-value resistors. This would require large area on the chip and consume relatively large powers. The full-flash ADC is, therefore, considered to practical only for relatively small number of bits. Fortunately, using the concept of folding ADC can reduce the number of active and passive components of flash ADC with a reasonable cost in terms of reducing the conversion speed of the ADC. In a folding ADC a folding amplifier must be used. In order to avoid the use of correcting circuits to reduce the errors resulting from the folding process, it is preferable to use a folding amplifier with sawtooth input–output characteristics.
A full input range, 1–1.8 V voltage supply scalable analog voltage comparator in 180nm CMOS
Published in International Journal of Electronics, 2021
Ashima Gupta, Anil Singh, Alpana Agarwal
Figure 12 shows the transient analysis of 5-bit flash ADC using the proposed comparator. Here, a ramp signal is given to ADC and M0-M4 are its digital output bits. The FFT response of 5-bit flash ADC is obtained for an input signal frequency of 24.21 MHz when sampled at 400 MHz and shown in Figure 13. The archived values of SFDR, SNDR, ENOB and SNR are 38.96 dB, 30.59 dB, 4.78 and 31.27 dB, respectively. The total power consumed by 5-bit flash ADC is 6.14 mW as shown in Figure 14.
Power-Aware Testing for Maximum Fault Coverage in Analog and Digital Circuits Simultaneously
Published in IETE Technical Review, 2022
Vivek Kumar Singh, Trupa Sarkar, Sambhu Nath Pradhan
For a mixed-signal SOC, ADC is an essential building block. Among various types of ADCs, a flash ADC is a type of analog-to-digital converter that uses a linear voltage ladder with a comparator to compare the input voltage to successive reference voltages. Often these reference ladders are designed by many resistors. Flash converters are extremely fast and simple compared to many other types of ADCs. For best accuracy, often a track-and-hold circuit is inserted in front of the ADC input. This is needed for many ADC types (like successive approximation ADC), but there is no need for flash ADC because the comparators are the sampling devices. Here a 3-bit Flash ADC is designed using comparators. We can use a 4-bit FLASH ADC instead of 3-bit one but one of our testing circuits having only 9 inputs from which 3 fixed inputs are taken from ADC’s output for a particular analog signal and 6 external control inputs are available for the GA. Also if we go for a 4-bit ADC, then the complexity and area will increase for the design. As we are focusing on mixed-signal SOC testing we have taken ADC as fault free and the output of ADC to compare the fault-free circuit and the faulty circuit using one signature circuit. In this work a fine comparator is used instead of a coarse comparator in the design of ADC. The fine comparator has a large area, but less least significant bit (LSB) noise effect than the coarse comparator and the LSB noise can be reduced to of the coarse comparator [17]. So, in this work, in the design of ADC, fine comparators are used. This reduces the toggling in the LSB of ADC. ADC with a fine comparator has been designed in the cadence virtuoso 45 nm technology and noise because toggling has been verified. The output of the ADC that uses the fine comparator is given in Figure 3 for the justification.