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Analog and Digital VLSI Design
Published in Bogdan M. Wilamowski, J. David Irwin, Fundamentals of Industrial Electronics, 2018
A comparator is a decision-making circuit that compares two analog voltages and generates a corresponding digital output. The output is high if the analog input at the positive terminal (vin+) is larger than the signal at the negative input terminal (vin–) and low for the opposite case. Figure 19.22 shows the implementation of a clocked comparator realized from a basic cross-coupled latch. If an imbalance is created between the two nodes, A and B, the voltage difference between the two is amplified by the inverters. Thus, if initially node A is at higher voltage than node B, the voltage at node A will continue to increase until it settles close to VDD and node B settles near the ground. The latch is modified to make decision when the clock (CLK) goes high by adding a clocked switch to turn the latch on when the clock is high. Another switch is employed to erase the comparator memory from the previous decision by equilibrating the nodes A and B when CLK is low.
Sensors
Published in Volker Ziemann, A Hands-On Course in Sensors Using the Arduino and Raspberry Pi, 2018
A close relative to the operational amplifier is the comparator. It can be visualized as an op-amp with very large, even infinite, amplification, whose output port saturates at the power rails. If the voltage at the positive input terminal of a comparator is larger than that on the negative input terminal, the output voltage is very close to the positive supply voltage. On the other hand, if the voltage on the positive input terminal is lower than that on the negative, the output is close to ground potential. In this way it translates the input voltages to a binary digital state. A comparator may therefore be considered as a 1-bit analog-to-digital converter, and we will see in a later section how it is used to extend the number of bits of the conversion. Some comparators have the threshold when switching from low to high output configured to be slightly higher than the threshold switching from the high output state back to the low one. This small hysteresis prevents the output from switching back and forth uncontrollably, should the voltages on the two input terminal be very close.
Nanotechnology and Performance Development of Cutting Fluids
Published in Girma Biresaw, K.L. Mittal, Surfactants in Tribology, 2017
Nadia G. Kandile, David R. K. Harding, Girma Biresaw, K.L. Mittal
A comparator is a device that compares two voltages or currents and produces a signal indicating which is larger. The concept is based on a single point of contact with the sample being assessed for its thermal conductivity. The transfer of heat from the hot material to the cold is very quickly measured by such a device. The temperature difference between the probe tip and a reference in the heated probe is measured with a thermocouple. The probe (Figure 6.16a) is copper. The heater compensates for heat loss from the probe and allows for a constant temperature difference between sample and probe. The probe and sample material are connected by a constantan thermocouple. The constantan wire is made from a copper–nickel alloy usually consisting of 55% copper and 45% nickel and has constant resistivity over a wide range of temperatures.
Design and Optimization of Reversible Logic Based Magnitude Comparator Using Gate Diffusion Input Technique
Published in IETE Journal of Research, 2023
Dwip Narayan Mukherjee, Saradindu Panda, Bansibadan Maji
In advanced technology, the reversible logic is one among the simplest designing strategies for low power VLSI design. Since reversible logic is lossless, so this logic based circuit has no tendency to lose the information [1]. Consequently, the power consumption is lower in reversible logic gate based circuit design compared to other combinational logic gate based CMOS logic styles. The circuit design by combinational logic gates may lose the information by the dissipation of heat which is difficult to recover. The comparator has wide applications in digital signal processing, digital communication, sorting networks, encryption devices, etc. During this research work, various methodologies have been proposed to realize an optimized circuit design of the magnitude comparator in terms of constant input, garbage output, reversible gate, and quantum cost.
Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator
Published in IETE Journal of Research, 2023
Abhay S. Vidhyadharan, Gangavarapu Anuhya, Shivangi Shukla, Sanjay Vidhyadharan
If the input signal is almost equal to the reference level, in a noisy environment, noise can cause the input signal to make several transitions above and below the reference level, resulting in multiple transitions at the output, which in-turn can cause system error. These output glitches consume a huge amount of power. To eliminate these glitches, hysteresis is added to the comparator [4,18]. Hysteresis forces the threshold voltage required to switch the output to depend not only on the differential input but also on the previous input signal states. Comparator with hysteresis introduces two threshold voltages, one for the rising input signal and another for falling input signal. This is known as hysteresis characteristics or bi-stable characteristics. A common method to generate hysteresis is through positive feedback. Hysteresis comparators, therefore, are much more immune to noise and more power-efficient (due to reduced glitches) than the conventional comparators.
A low-power, low-offset, and power-scalable comparator suitable for low-frequency applications
Published in International Journal of Electronics, 2023
Riyanka Banerjee, M. Santosh, Jai Gopal Pandey
Comparator architectures are broadly classified into three types, that is, continuous-time, latched dynamic, and inverter-based. The continuous-time comparator and the latched dynamic comparator are based on differential input. Thus, any mismatch of the input transistor will result in an input offset, as given by Miyahara and Matsuzawa (2009). Latched dynamic comparators restrict static current, making them suitable for low-power and power-scalable applications, which is also mentioned by Schinkel et al. (2007). Some constraints restrict the performance of the switched capacitor latch comparator, such as offset, clock feedthrough, and kickback noise Figueiredo and Vital (2006). Kickback noise introduced by the high-swing output nodes corrupts the latched dynamic comparator output. A hybrid comparator has been reported in Lan et al. (2011), shows reduced kickback noise, while maintaining lower power consumption, but requires complex input offset cancelation techniques to achieve higher resolution Razavi and Wooley (1992). Since there is no static current flowing in the latched dynamic comparator Figueiredo and Vital (2006), it is an excellent choice for low-voltage and low-power designs. Architecture has been reported Figueiredo and Vital (2006) where a positive feedback mechanism has been incorporated to achieve high resolution and fast operation. However, a large voltage swing on the drain of a differential pair due to this current feeding through a drain-gate parasitic capacitor to the input node and the presence of source impedance results in kickback noise. ADC performance can be hampered by excessive kickback noise, which can eventually cause an incorrect comparator output as given by Lan et al. (2011).