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Semiconductors and Digital Logic
Published in Syed R. Rizvi, Microcontroller Programming, 2016
The truth table for a 2-input XNOR gate is shown in Table 2.15. Because of the inversion on the output side, the truth table of an XNOR gate is the complement of an XOR truth table. As shown in Table 2.15, the output is high when the inputs are the same. Therefore, the 2-input XNOR gate is ideally suited for bit comparison, recognizing when two input bits are identical. Helpful Hint: Instead of recognizing odd-parity words, XNOR gates recognize even-parity words.
Introduction
Published in Vlad P. Shmerko, Svetlana N. Yanushkevich, Sergey Edward Lyshevski, Computer Arithmetics for Nanoelectronics, 2018
Vlad P. Shmerko, Svetlana N. Yanushkevich, Sergey Edward Lyshevski
A logic network that compares two binary numbers and indicates whether they are equal, and/or indicates an arithmetic relationship (greater or less than) between the numbers, is called a magnitude comparator. The EXOR and XNOR gates may be viewed as 1-bit comparators. In particular, if the input bits are equal, then the output of the XNOR gate is 1, while otherwise it is 0 . Therefore, a straightforward implementation of an n-bit comparator can be accomplished using XNOR gates.
Simple System Design Techniques
Published in A. Arockia Bazil Raj, FPGA-Based Embedded System Developer's Guide, 2018
A portion of the function table for a 4-bit magnitude comparator is given in Table 3.4. Now, we will discuss how to analyze this 4-bit magnitude comparator and get its logical expression. Assume two inputs of 4-bit length as A[3:0], that is, A(3), A(2), A(1) and A(0), and B[3:0], that is, B(3), B(2), B(1) and B(0). When comparing the large binary or BCD numbers for equality, we can just use the xnor gate, that is, a combination of xor and not gates, as xor + not. Here, the xor gate will give logic 0 when the inputs A and B are equal, and an inverter, that is, a not gate, complements it. Hence, the xnor gate output is logic 1 if both inputs are equal. For A > B, to save time, the comparator has to start comparing the highest-order bit, that is, the MSB bit, first as (A(3) and not B(3)). Here, if A(3) is logic 1 and B(3) is logic 0, then the result of this expression is logic 1; thus, A > B. If equality exists at A(3) and B(3), then we need to compare the next lowest bit as [(A(3) xnor B(3)) and (A(2) and not B(2))]. Here, the first part is for the equality of A(3) and B(3), and the second part is for A(2) > B(2); thus, the result is A > B. If the equality still exists, then we have to continue until it reaches the lowest-order bit, i.e., the LSB. In the same way, the logical expression for A < B can be obtained. The Boolean expressions for A = B, A > B and A < B are: Eq = (A xnor B)Ag = [(A(3) and not(B(3))) + ((A(3) xnor B(3)) and (A(2) and not(B(2))) + ((A(3) xnor B(3)) and (A(2) xnor B(2)) and (A(1) and not(B(1))) + ((A(3) xnor B(3)) and (A(2) xnor B(2)) and (A(1) xnor B(1)) and (A(0) and not(B(0)))]Al = [(B(3) and not(A(3))) + ((B(3) xnor A(3)) and (B(2) and not(A(2))) + ((B(3) xnor A(3))and (B(2) xnor A(2)) and (B(1) and not(A(1))) + ((B(3) xnor A(3)) and (B(2) xnor A(2))and (B(1) xnor A(1)) and (B(0) and not(A(0)))]
Multi-input volistor logic XNOR gates
Published in International Journal of Parallel, Emergent and Distributed Systems, 2020
Muayad J. Aljafar, Marek A. Perkowski, John M. Acken
This section describes an implementation of a multi-input XNOR gate using the proposed two-input XNOR gate. An N-input XNOR gate is widely used in arithmetic, security, testing, and communication circuits. This gate can be implemented by cascading 2-input volistor logic XNOR gates in two crossbar arrays. Figure 6 shows a block diagram of an N-input XNOR gate that consists of 2-input XNOR gates (XNOR1 and XNOR2) connected through CMOS switches. The XNOR gate is configured as a function of signals 1–7, X, Y, and Z. (See Figure 6 to identify the terminals). Table 5 explains the operation of the circuit. For example, in the first clock cycle, XNOR1 and XNOR2 are set to logic ‘1’. In the second clock cycle, XNOR1 implements XNOR (Vin1, Vin2). In the third clock cycle, XNOR2 implements XNOR (Vin1, Vin2, Vin3), and in the fourth clock cycle, XNOR1 is set to logic ‘1’ to realise XNOR (Vin1, Vin2, Vin3, Vin4) in next clock cycle. This process continues until an N-input XNOR gate is realised. In each clock cycle, a combination of control or input signals is applied to the circuit to perform a particular operation. For example, in the first clock cycle, signals XYZ are at logic ‘110’, terminals 1, 2, 4, 5, and 7 are set to 0 V, and terminals 3 and 6 are connected to VSET. In particular, during the write operation, VDSEL is applied to terminal 4 or terminal 7 to avoid any state transition in AND gate memristors. The computational delay of the circuit is 2N−3 where N ≥ 4. Table 5 also shows the states of XNOR1 and XNOR2 as a function of multiple signals. When XNOR1 (or XNOR2) is in state ‘−’, it waits for XNOR2 (or XNOR1) to complete the setting or write operation. In clock cycle number seven, XNOR1 and XNOR2 repeat their states as they were the third clock cycle. Table 6 summarises the size and delay comparisons of different N-input memristive XOR/XNOR circuits. Some of these comparisons are based on published data [3] while others are based on our generalisation of two-input XOR/XNOR gates [4,7]. The proposed N-input volistor logic XNOR circuit is small and relatively fast.