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NoC and System-Level Design
Published in Hoi-Jun Yoo, Kangmin Lee, Jun Kyoung Kim, Low-Power NoC for High-Performance SoC Design, 2018
Hoi-Jun Yoo, Kangmin Lee, Jun Kyoung Kim
In the conventional hardware design, the designers themselves had to understand detailed specification of the target system, divide it into multiple manageable subsystems, and implement the target system based on their own experience in hardware design. On the contrary, system design with an object-oriented method begins with use case analysis. This is a process to define the system requirements in the form of use case diagrams, starting from basic functions of the system and proceeding to other related functions. In addition, it is possible to make a clear distinction between the system and the system interface, and to provide a detailed description of the external input and output functions. Figure 1.9 shows a use case diagram for the SD memory card. To describe the use of the target system, in the first place, the type of user, such as “actor,” who controls the operation of the system should be specified. If a digital camera reads or stores data through SPI, the camera is placed in the left side of the use case diagram as an actor. Its basic functions are to read data and to store data operations, as shown in Figure 1.9. For data storage, parallel data is converted into serial data, and the logical address of the host memory space is transformed into the physical address of the NAND Flash memory. In this example, wear-leveling is adopted to prevent the Flash memory block from wearing out [6]. In addition, comments can be added to explain each use case diagram in more detail.
Spin-Transfer Torque RAM
Published in Hai Li, Yiran Chen, Nonvolatile Memory Design, 2017
Wear leveling is a method that can help to prolong the memory system lifetime by evening out the write distribution of a memory system; for example, cache or main memory. A wear leveling scheme can be implemented at different granularities and has been studied extensively for flash-based memory or PCM-based memory [26, 31, 32, 41]. These wear leveling schemes can also be implemented in STT-RAM-based storage. The most common wear leveling scheme uses tables to record the access counts on each access unit; for example, a block. Periodically, the most accessed blocks are logically remapped to the least accessed blocks. A separate table is used to record the logical to physical mapping information of these blocks. Usually a wear leveling scheme suffers from significant storage overhead and increasing latency.
Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
Published in IETE Technical Review, 2023
Sadhana Rai, Basavaraj Talawar
Lifetime improvement by a uniform distribution of writes among all the cells is one method that can enhance the lifetime of the NVM devices. Some applications exhibit non-uniform write behavior, which can reduce the lifetime of a few cells and may eventually lead to the failure of the entire memory. Wear leveling methods map frequently written cells to less often reported areas. Many wear leveling techniques have been proposed in the past, which can be broadly classified into two categories age-based methods and randomization-based methods [84]. Age-based methods swap severely written NVM areas with less frequent areas by keeping track of write counts. Whereas randomized methods perform writes randomly in some memory regions. Most of the wear leveling techniques are designed for write operations but few NVM devices like FeRAM suffer from destructive reads as well, in such cases, wear leveling is essential for read operations. Wear leveling for read operation was proposed in Ref. [85]. This method used a software-based wear leveling approach by using the age of the page as criteria for performing wear-leveling based on read-write accesses. Information about read-write accesses is stored in the form of a red-black tree. This approach could make lifetime by up 955×, and for read destructive NVMs, up to a factor of 418× without using any dedicated hardware. Most of the age-based schemes use sampling-based approach to get the age of the pages, a recent technique lamina [84] is designed to handle wear leveling at the bounded tail level. This approach enhanced NVM’s lifetime by 81.4× on an average with low overhead. It avoids the bounded tail wear-out problem by maintaining the wear limit of all pages to an average value. Another prevalent technique is multi-way wear leveling (MWWL), the logical address space is divided into sub-regions, and then wear-leveling is applied for each region [86]. Wear-leveling is an essential factor to be considered while deploying NVM devices as memory devices. Several wear-leveling mechanisms are already developed, as mentioned in this subsection. A good wear-leveling technique should be able to handle writes with minimal overhead.