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Head-Up Display
Published in Cary R. Spitzer, Uma Ferrell, Thomas Ferrell, Digital Avionics Handbook, 2017
Robert B. Wood, Peter J. Howells
Video processing is used to optimize the received video image for display to the pilot on the HUD. This may include any or all of the following: Converting from a raster scan to a digital image to eliminate the overscan and flybackConverting analog video to a monochrome digital pixel imageApplying image improvement algorithms to enhance image contrast and reduce image noiseUpscaling from the raw image resolution to the resolution of the HUD image source
An Overview of Affective Computing from the Physiology and Biomedical Perspective
Published in Spyrou Evaggelos, Iakovidis Dimitris, Mylonas Phivos, Semantic Multimedia Analysis and Processing, 2017
Ilias Maglogiannis, Eirini Kalatha, Efrosyni-Alkisti Paraskevopoulou-Kollia
Finally, video processing is a special case of signal processing, where input and output signals are video files or video streams. It is worth mentioning that in [387] the existence of a number of early efforts to detect nonbasic affective states, such as attentiveness [309], fatigue [385], and pain [104] from face video, is described.
Video compression using improved diamond search hybrid teaching and learning-based optimization model
Published in The Imaging Science Journal, 2023
B. Veerasamy, B. Bharathi, A. Ahilan
Motion estimation is one of the most challenging aspects of video compression. There are numerous applications for it, including robot navigation, visual tracking, mixed and expanded reality, image and video processing and astute transportation systems [1]. In day-to-day life every individual maintains different types of records in their daily lives, such as TV multimedia applications, web files and so on. Because the file format is too big, video signal power and delivery are difficult tasks in video processing. It necessitates a file compression strategy capable of packing the film with minimal data loss [2]. Compression requires several mappings, the identification of acceptable pixels that can be minimized, the identification of comparable pixels and assistance in further data reduction without losing its impact on the total amount of data [3]. Several studies have been conducted in the last number of generations to create reliable videos that can pack data without error [4]. The crude unprocessed movie includes an enormous amount of data, yet memory space is costly and constrained.
Artificial hummingbird optimizer as a novel adaptive algorithm for identifying optimal coefficients of digital IIR filtering systems
Published in International Journal of Modelling and Simulation, 2023
Serdar Ekinci, Davut Izci, Murat Kayri
Digital filtering has a significant role in system identification and signal processing-related applications such as digital communication, video processing, image processing and digital signal processing. It is feasible to perform the desired tasks either via finite impulse response (FIR) or infinite impulse response (IIR) filters [1]. However, the use of the digital IIR filters is more common due to having less ordered structure and smaller group delay along with providing less cost and more accurate approximations [2]. The design procedure of the IIR digital filters via gradient-based traditional routes takes longer time and costs higher computational loads due to nonlinear and multimodal error surfaces which has a direct link with the filter coefficients [3,4]. Therefore, the researchers have started to investigate cost effective solutions in order to overcome the aforementioned difficulties [5]. In this context, the metaheuristic optimization procedures have been heavily adopted as effective, powerful, and practically more convenient solutions [6–9].
Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node
Published in Australian Journal of Electrical and Electronics Engineering, 2023
Umayia Mushtaq, Md Waseem Akram, Dinesh Prasad
In our analysis, it can be implemented to design FinFET adder circuits. This technique provides a better trade-off between power dissipation and propagation delay in digital logic circuits. This technique does not increase propagation delay to a large extent as in the case of stacked transistors due to proper input terminal selection of INDEP transistors. In almost every field of VLSI, microprocessors, digital signal processing, image and video processing, the arithmetic operations like addition, subtraction and multiplication are frequently used. For this, the major candidates are the circuits with low leakage power. Therefore, the basic building blocks like full adders and half adders need to be designed in such a way so as to minimise leakage besides improving other performance parameters as well (Sadeghi and Golmakani 2014).