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RISC Architecture
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
The UltraSPARC is a super pipelined superscalar processor enriched with some salient features, not available with ordinary SPARC. Superscalar processor consists of two independent pipelines: each pipeline consists of nine stages, and each stage is completed strictly in one processor clock cycle. Each pipeline consists of two execution units: one for integer operations with its own register set and one for floating-point operations having its own different register set, and they can be operated simultaneously in parallel through its own pipeline. As a result, a total of four new instructions can enter the execution phase every clock cycle. The processor uses two levels (multilevel) of cache: an external cache (E-cache) and two internal caches, one for instruction (I-cache) and one for data (D-cache). The MMU has two translation lookaside buffers (page table storage): one for instructions (iTLB) and one for data (dTLB). The UltraSPARC series of processors handles both addresses and data as 64-bit values, but maintains downward compatibility to accommodate everything of earlier 32-bit versions. A recent release, the UltraSPARC III fabricated with 0.18-µm technology having a clock speed in the range of 750–900 MHz, is enriched with many useful advanced features. It is targeted to attain around 1.5 GHz in the forthcoming days.
The facility layout instances of the generalised travelling salesman problem
Published in International Journal of Production Research, 2021
Ardavan Asef-Vaziri, Morteza Kazemi, Maryam Radman
We now present our computational considerations. We have used the general-purpose MIP solver IBM ILOGCPLEX V12.1 to solve the problem. All computations were carried out on a Sun Microsystems Ultra 10 workstation with a 440 MHz UltraSPARC-IIi processor and 128 MBytes of RAM, running the Solaris 8 operating system. We computationally compare the optimal global solution with (i) Sh-loop, (ii) MNC-loop, and (iii) the I-MNC-loop. We show that the complementary heuristics developed in the space between (i) and (iii) provide promising solutions to minimise the total loaded and empty flow in AGVSs.