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The CPU
Published in Mike Tooley, Aircraft Digital Electronic and Computer Systems, 2023
When the time comes to suspend a particular task in order to briefly attend to something else, most microprocessors make use of a region of external random access memory (RAM) known as a stack. When the main program is interrupted, the microprocessor temporarily places in the stack the contents of its internal registers together with the address of the next instruction in the main program. When the interrupt has been attended to, the microprocessor recovers the data that has been stored temporarily in the stack, together with the address of the next instruction within the main program. It is thus able to return to the main program exactly where it left off and with all the data preserved in its registers. The stack pointer is simply a register containing the address of the last used stack location.
Microprocessors
Published in Mike Tooley, Electronic Circuits, 2019
When the time comes to suspend a particular task in order to briefly attend to something else, most microprocessors make use of a region of external random access memory (RAM) known as a stack. When the main program is interrupted, the microprocessor temporarily places in the stack the contents of its internal registers together with the address of the next instruction in the main program. When the interrupt has been attended to, the microprocessor recovers the data that have been stored temporarily in the stack together with the address of the next instruction within the main program. It is thus able to return to the main program exactly where it left off and with all the data preserved in its registers. The stack pointer is simply a register that contains the address of the last used stack location.
The central processing unit
Published in D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader, Mechatronics, 2018
D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader
As an example, consider the operation of the stack during execution of the JSR instruction. For an 8 bit CPU with a 16 bit address bus, the return address must be written to and read from the stack as two bytes. Assuming that the stack grows upwards in memory, when the JSR instruction is executed, the contents of the PC, which is the address of the following instruction, are written to the top of the stack using two write cycles. After each write cycle the stack pointer is incremented to point to the top of the stack. When the RTS instruction is executed at the end of the subroutine, the exact reverse procedure is followed in order to restore to the PC the address of the instruction following the JSR instruction. This time, two read cycles are required and the contents of the SP are decremented before each read cycle.
Multi-model predictive control of Hammerstein-Wiener systems based on balanced multi-model partition
Published in Mathematical and Computer Modelling of Dynamical Systems, 2019
Jingjing Du, Lei Zhang, Junfeng Chen, Jian Li, Changping Zhu
Step 3: Divide the scheduling space Φ into several monotone intervals according to the variation of the scheduling variable. For example, yN is chosen as the scheduling variable. Here we get 3 monotone intervals [yN1, yN2], (yN2, yN3], (yN3, yN4]. And pick out the left and right terminal points of every monotone interval as initial gridding points. Namely, the initial value is [yN1, yN2, yN3, yN4]. Then, put the left terminal point of the 1st monotony range α1 into queue Qθ, so we have Qθ = yN1. Set α = yN1, and push the other initial points into stack Sθ, Sθ = [yN2, yN3, yN4]. The stack pointer is denoted as top. Set β = yN2.
Profile-guided optimisation for indirect branches in a binary translator
Published in Connection Science, 2022
Jyun-Siang Huang, Wuu Yang, Yi-Ping You
AArch64 is the 64-bit execution state in ARMv8 (ARM, 2013). The instruction set which is supported in the AArch64 execution state is known as A64. Each A64 instruction is encoded in 32 bits. AArch64 provides 31 64-bit general-purpose registers, a 64-bit Stack Pointer register (SP), a 64-bit Program Counter (PC), 32 128-bit SIMD and floating-point registers (ARM, 2013).