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Fundamental Computer Architecture
Published in Jerry C. Whitaker, Microelectronics, 2018
The first component (computations/instruction) measures the complexity of the instructions being executed and varies according to the structure of the processor and the types of instructions currently being executed. The inverse of the component (instructions/cycle) is commonly quoted for single processor designs as cycles per instruction (CPI). The inverse of the final component (cycles/second) can also be expressed as the clock period of the processor. In a RISC processor, only hardware for the most common operations is provided, reducing the number of computations per instruction and eliminating complex instructions. At compile time, several basic instructions are used to execute the same operations that had been performed by the complex instructions. Thus, a RISC processor will execute more instructions than a complex instruction set computer (CISC) processor. By simplifying the hardware, the clock cycle is reduced. If the delay associated with executing more instructions (RISC design) is less than the delay associated with an increased clock cycle for all instructions executed (CISC design), the total system performance is improved. Improved compiler design techniques and large on-chip caching has continued to contribute to higher performance RISC designs (Hennessy and Jouppi, 1991).
The central processing unit
Published in D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader, Mechatronics, 2018
D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader
While a RISC CPU may execute instructions faster and cost less than a CISC, its individual instructions are much simpler, so that it would have to execute several instructions in order to perform the equivalent function of a single CISC instruction. In addition, the RISC will require more memory to store the extra instructions, so that at the end of the day there may be little to choose between a RISC microprocessor and a CISC microprocessor. The trend today is to produce microprocessors that implement the benefits of both philosophies, so that an instruction set will consist of a core of frequently used instructions capable of executing in a single cycle, with additional more complex instructions to improve the functionality of the instruction set.
Computers in communications
Published in Geoff Lewis, Communications Technology Handbook, 2013
RISC processor. The term RISC is an acronym of reduced instruction set computer, as opposed to the corresponding term complex instruction set computer (CISC) which was coined to differentiate between the two concepts. Throughout most of the period of computer development, an increase in computer power has been achieved by increasing the number of operations that it could perform together with increasing its clock frequency. As the complexity of the operations increased, so did the time taken for the processor to search through its operation code list that was stored in microcode (see also Programming languages, p. 72) in its memory. Research has shown that the computer uses its operation code set almost on an 80/20 basis. That is, for 80% of its calculations it uses only 20% of its instruction set. Thus the RISC chips developed along with the Harvard architecture, allowing the computations to be carried out within the registers, with processing requiring the minimum number of operation codes, each of which is directly executable without the need for decoding. Complex instruction can then be carried out, either by being built up from a series of simple operations, or from decoding logic that is hardwired into the silicon of the chip. By using a pipeline that is maintained full by on-chip data and instruction caches, most operations are carried out in a single clock cycle so that the RISC processor can run 2 to 5 times faster than the CISC chip. A memory management unit (MMU) chip is required to look after the transfers between the processor and the main memory. The concept was developed chiefly for high level language applications and this in turn has produced a demand for optimised compiler languages (see also Programming languages, p. 72).
Profile-guided optimisation for indirect branches in a binary translator
Published in Connection Science, 2022
Jyun-Siang Huang, Wuu Yang, Yi-Ping You
RISC-V is a novel open-source RISC instruction set architecture. It provides various standard extensions. Some extensions are shown in Table 1. RISC-V base integer instruction set is a load-store architecture, where memory is only accessed by load and store instructions and arithmetic instructions only operate on registers (Waterman & Asanović, 2019). RISC-V has 31 general-purpose registers and a program counter (PC).