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Spin Nanoscale Electronic Devices and Their Applications
Published in Khurshed Ahmad Shah, Farooq Ahmad Khanday, Nanoscale Electronic Devices and Their Applications, 2020
Khurshed Ahmad Shah, Farooq Ahmad Khanday
MTJ is one of the most promising spintronics devices and applied as the basic memory cell in MRAM and magnetic logic development. It is a non-volatile FM device, which is formed by sandwiching of two FM material layers with a fixed layer pinned to constant direction with other pointing bi-directional free layer/storage layer, as depicted in Figure 6.3. These FM layers are separated by thin non-magnetic insulating material. The insulating material is so thin that electrons can travel through it by tunneling. The spin polarization in the pinned layer and storage layer is in the same or opposite direction. The configuration of the MTJ stack can be switched simply by altering the spin magnetization direction of the storage layer, which may be induced by the magnetic field with opposite direction and superior than the threshold value. The phenomenon of change in resistance due to an externally applied field is explained by tunnel TMR effect. To support fast writing speed and high efficiency in terms of power, one of the promising switching techniques is spin transfer torque (STT) in which the orientation of magnetization can be modified using a spin polarized current [21]. This basic physical technique enables simplifying CMOS circuitry. It also presents the advantages of lower threshold current and hence low-power, higher-speed operation, scalability, and high endurance [4].
Spin Torque Effects in Magnetic Systems
Published in Evgeny Y. Tsymbal, Žutić Igor, Spintronics Handbook: Spin Transport and Magnetism, Second Edition, 2019
The present chapter is focused on the spin-transfer-torque (STT) phenomenon which refers to a novel method to actively control and manipulate magnetic moments, or spins, using an electrical current. This method offers unprecedented spatial and temporal control of spin distributions and attracts a great deal of attention because it combines interesting fundamental science with the promise of applications in a broad range of technologies. STT effect is sometimes regarded as inverse to the giant magnetoresistance (GMR) effect, in that the magnetic state of a GMR structure affects its transport properties, while transport currents can alter the magnetic state via STT. This intimate connection can be traced throughout both theoretical and experimental studies of STT and makes GMR, examined in the previous chapters, a most excellent foundation for our discussion. Here we will focus on various aspects of STT experiments in metallic systems including device fabrication and STT detection techniques. In what follows we introduce the basic physics of STT effect in magnetic metallic multilayers. For additional details on STT theory in metallic systems, we refer to the next chapter of this book. STT in magnetic tunnel junctions and semiconductors will be discussed in sections III and IV, respectively.
Perpendicular Spin Torque Oscillator and Microwave-Assisted Magnetic Recording
Published in Xiaobin Wang, Krzysztof Iniewski, Metallic Spintronic Devices, 2017
One of the fundamental physics concepts behind magnetoresistance effects is the fact that an electron current carries a net spin angular momentum after passing through a magnetized ferromagnetic film. When a spin-polarized current interacts with a local magnetization by exerting a torque on the localized spins, referred to as spin-transfer torque (STT), the orientation of the magnetization could be altered. Following pioneering theoretical work [5, 6], an experimental demonstration in 1999 showed the world for the first time that a spin-polarized current, other than a magnetic field, can be used to switch the magnetization of a ferromagnetic film [7], as many other experiments showed later [8, 9]. Magnetoresistive random access memory (MRAM) based on the STT effect, referred to as STT-MRAM, was quickly proposed along with research and development efforts [10–17]. An MgO-based magnetic tunnel junction has been used as a memory element for both the in-plane magnetization mode and perpendicular magnetization mode [18–20].
Neural network detector with sparse codes for spin transfer torque magnetic random access memory
Published in Cogent Engineering, 2023
Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising technologies for next-generation non-volatile memory (NVM) systems. Flash and dynamic RAM (DRAM) are now leading in electronic memory. However, the problem of the write/erase (W/E) cycles is hugely challenging for Flash systems. The reliability of the device is significantly degraded due to the W/E being over the limit. Moreover, DRAM cannot provide a non-volatile feature and has high power consumption due to the significant effect of inevitable leakage current. The STT-MRAM has arrived as a leading candidate for stand-alone and embedded NVM applications among various emerging NVM technologies (H. Cai et al., 2021). Significantly, due to attractive advances such as durable and non-volatile devices or nanosecond read and write processes, the STT-MRAM is very useful in many applications, such as consumer electronics devices, cache in mobile devices, and IoT/AI devices.
An Energy-Efficient Hybrid Tunnel FET based STT-MRAM Memory Cell Design at Low VDD
Published in International Journal of Electronics, 2022
Sudha Vani Yamani, N. Usha Rani, Ramesh Vaddi
Spin Transfer Torque Magnetic Random-Access Memory (STT-MRAM) devices achieve non-volatility, energy efficiency, high endurance and high density in comparison to electrical charge based conventional memories (Chen et al., 2009; Hosomi et al., 2005; Kang et al., 2015; Tu et al., 2012). The poor scalability of STT-MRAM devices requires high ON current and high VDD values to change the states effectively and this led to reduction in energy efficiency. To further increase energy efficiency of STT-MRAMs, various CMOS write circuit techniques such as write completion circuits, self-adaptive write circuits, and self-terminated write assistant circuits were proposed (Farkhani, Peiravi, Madsen et al., 2015; Park et al., 2015; Suzuki et al., 2014). However, the implementation of these techniques incurs area overhead. Similarly, many other techniques such as usage of negative bit line (Farkhani, Peiravi, Moradi et al., 2015), 2 T-1 R double source line bit-cell technique (Suzuki & Hanyu, 2015), and asymmetric doping at the source/drain (S/D) terminals (Choday et al., 2014) were proposed to reduce the cell energy consumption. Chen et al. (2019) developed a Euler–Lagrange equation for write energy optimisation of STT-MRAM, Garzón et al. (2020), Natsui et al. (2019), Puebla et al. (2020), Sverdlov et al. (2020) demonstrate various energy-efficient techniques for STT-MRAM-based applications. All above designs are based on CMOS designs and exhibit asymmetrical switching time and high write energy consumption.
Cache performance of NV-STT-MRAM with scale effect and comparison with SRAM
Published in International Journal of Electronics, 2022
Zitong Zhang, Wenjie Wang, Pingping Yu, Yanfeng Jiang
Therefore, an alternative method is needed to solve the problem of the oversized of the cache memory and the overloss of the power, especially when the MOSFET feature size shrinks down into nanometres. The development of non-volatile memory technology has become an effective solution to this problem. Among the existing non-volatile memory technologies, the Spin Transfer Torque Magnetic RAM (STT-MRAM) is characterised by its small size, non-volatile, high read speed, low leakage, and compatible CMOS technology. It shows the possibility to satisfy the requirements of the cache in CPU (Lin et al., 2009). STT-MRAM is an advanced MRAM with higher densities, low leakage current and lower cost than SRAM. The cell area of STT-MRAM is about 10 times smaller than SRAM. Its endurance is reported to be infinite. The size of an STT-MRAM cell can be scaled down to 10 nm while keeping good performance. STT-MRAM has the potential to become the next generation of storage technology. As its manufacturing process is better compatible with the CMOS technology, STT-MRAM shows a promising tendency to take the place of SRAM and DRAM. However, until now, there are also disadvantages that cannot be ignored on STT-MRAM, such as high write delay and high leakage power of HP devices. In recent years, besides the STT-MRAM, another MRAM, named spin-orbit-torque magnetic RAM (SOT-MRAM), has also attracted widespread attention as one of the possible candidates for the MRAM technology. SOT-MRAM is based on the three-terminal magnetic tunnel junction and uses Spin Hall Effect for the switching. It attempts to overcome the high write latency and the energy of STT-MRAM by separating the read path from the write path (Cheshmikhani et al., 2020). However, SOT-MRAM needs two transistors for read and write operations. This makes the area of SOT-MRAM far exceed the area of STT-MRAM in the cache application, especially in the large capacity scenario. On the other hand, SOT-MRAM is an emerging research direction with promising performance, with promising applications in the field of future memory chip.