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Emerging Non-volatile Memories
Published in Shimeng Yu, Semiconductor Memory Devices and Circuits, 2022
In 2017, Intel and Micron jointly announced the commercialization of 3D X-point technology based on PCM and OTS, resulting in Optane and X-100 high-end solid-state drive (SSD) products, respectively. As shown in Figure 5.24, the first-generation design is a 2-layer integrated cross-point array with 20 nm half pitch, where the peripheral CMOS circuits are hidden underneath the array. A reverse engineering report (by Tech Insights [19]) revealed that the PCM is based on GST material, and the OTS is based on Ge-Si-Se-As alloy. The commercial chip has a capacity of 128 Gb, a write bandwidth of 35 GB/s, and a read cycle time of 100 ns, making it competitive to be storage class memory between the DRAM and the NAND Flash. A more intuitive metric is the integration density in terms of Gb/mm2, the first-generation 3D X-point is 0.62 Gb/mm2, while contemporary DRAM products (e.g., in 1x nm node) is about 0.19 Gb/mm2 and contemporary 3D NAND product (e.g., 64-layer with TLC) is 5.6 Gb/mm2. In 2020, Micron announced a cease of further 3D X-point technology development, while Intel reported a second-generation of 3D X-point which has a 4-layer cross-point array.
Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
Published in IETE Technical Review, 2023
Sadhana Rai, Basavaraj Talawar
Intel Optane is PCM-based memory that is commercially available, and it is also familiar as 3D-XPoint, it is 3D stack-able transistor with less memory; it provides a good density of around 4.5x times larger than 20 nm DRAM and good endurance (108−109) [44,45]. Besides these options, choosing the candidates for hybrid memory and finding the proportionate amount of each memory is a challenge for memory designers. Stacked DRAM technologies provide higher bandwidth but with lower capacity, while non-volatile memories enable us to create cost-effective hybrid memories with a large capacity [14,48,49]. In this paper, we majorly discuss about the issues in organizing hybrid memories comprising of DRAM and NVM.