China
Africa
Explore chapters and articles related to this topic
From Circuit Schematics to PCB
Published in Julio Sanchez, Maria P. Canton, Embedded Systems Circuits and Programming, 2017
Julio Sanchez, Maria P. Canton
Along these same lines, a consortium of universities and circuit fabricators developed the Metal Oxide Semiconductor Implementation Service, (or MOSIS.) The system was used to train students by producing real, integrated circuits that were low-cost, reliable, and based on relatively simple technologies. In the early 1980s, electronic design tools ceased to be developed internally by the circuit development companies and became a separate business and technology. The term EDA, for Electronic Design Automation, was coined at this time and the first design automation conference took place in 1984. Several specialized programming languages were developed during this period for the hardware design and description of electronic circuits. Verilog, developed by a private enterprise, and VHDL, by the US Department of Defense, are among the best known. Simulators based on these languages also became available.
Application-Specific Integrated Circuits
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
M. Michael Vai, William S. Song, Brian M. Tyrrell
MOSIS is a low-cost prototyping and small-volume production service established in 1981 for commercial firms, government agencies, and research and educational institutions around the world (see the MOSIS website at http://mosis.org for more information). Most of these clients do not have volume large enough to form an economically meaningful relationship with a silicon foundry.
Efficient recursive least squares parameter estimation algorithm for accurate nanoCMOS variable gain amplifier performances
Published in International Journal of Electronics, 2020
Houda Daoud, Sawssen Lahiani, Samir Ben Salem, Mourad Loulou
The CMOS technology continues to develop and leads to wonderful benefits to consumers and businesses. In fact, the Bulk CMOS is the dominant transistor for integrated circuit design, thanks to its tremendous scalability which will arguably continue towards the 10 nm regime. During the technology scaling, the transistor performance is sensitive to some critical primary parameters including the supply voltage (Vdd), the threshold voltage (Vth), the electrical oxide thickness (Tox), the drain and the source parasitic resistance (Rdsw), the mobility (μ), the channel doping concentration (Nch), … ect. In this section, we focused on predicting the primary parameters of CMOS transistor for an upcoming process (16 nm, 12 nm and 10 nm) using the Bisquare Weights (BW) method and a novel recursive least squares (RLS) parameter estimation algorithm. The use of both of estimation methods requires predefined (xi, yi) scatter. xi and yi parameters represent respectively the process nodes and the transistor parameters. Nowadays, device engineers are seriously focusing on nanometre design field. In fact, the Predictive Technology Model (PTM) represents an initial attempt in this issue. It computes the device process and physical parameters (Nch, Esat, K, μ and Vsat) and generates the corresponding PTM model files for downscaling process nodes. It is a successful and efficient strategy. Knowing the accuracy of the PTM predictions and relying on the standard BSIM model, the PTM aims to achieve technologies scaling down to 22 nm node. A second effort is the Metal Oxide Semiconductor Implementation Service (MOSIS) which offers access to a wide variety of a semiconductor process for different process nodes. Table 1 presents some technological parameters of the MOS transistor for different process nodes varying from 250 nm to 22 nm. According to the literature, these parameters are chosen based on the PTM and the MOSIS sources (Cao, 2011; Minaei & Yuce, 2010). From this table, we considered the (xi, yi) scatter which would fit by a mathematical model.