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Embedded Systems Design
Published in Zdravko Karakehayov, Knud Smed Christensen, Ole Winther, Embedded Systems Design with 8051 Microcontrollers, 2018
Zdravko Karakehayov, Knud Smed Christensen, Ole Winther
The second group of tools, classified as prototype related, can be used for design verification when a prototype is available. We can further subdivide them into processor independent tools and tools which are related to a specific machine. A tool which is particularly valuable when we emphasise the digital interface and its history, is called a logic analyzer [Clem 1987]. The basic principle behind the logic analyzer is recording the signals over a certain time interval and then displaying them on the screen. Hence, the logic analyzer has two modes: an acquisition mode and a display mode. The samples are stored in the memory as digital signals, regardless of the fact that the real voltages could be somewhere in the middle. The collected data can be displayed either as a table or by waveforms. In addition, if the target address and data buses are sampled, a mnemonic presentation would be possible. In this case, the analyzer must possess a module for the target microcontroller. This will allow the analyzer to disassemble the code.
Digital Test Equipment and Measurement Systems
Published in Jerry C. Whitaker, Electronic Systems Maintenance Handbook, 2017
The logic analyzer is used routinely by design engineers to gain an in-depth look at signals within digital circuits. A logic analyzer can operate at 100 MHz and beyond, making the instrument ideal for detecting glitches resulting from timing problems. Such faults are usually associated with design flaws, not with manufacturing defects or failures in the field.
A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS
Published in International Journal of Electronics, 2019
Long Zhao, Bao Li, Yuhua Cheng
The proposed ADC targets embedded SoC applications, where the output digital code stream will be transferred on-chip. To avoid the complex high-speed I/O design and facilitate the ADC IP core testing, a 25-kbit on-chip memory is designed. This test-assistant memory relaxes the speed requirement for the testing equipment such as logic analyzer and removes the risks of propagating 10 Gb/s data on a PCB, such as power integrity, cross-talk, and signal integrity problems (Radulov, Quinn, & van Roermund, 2015).