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Basics of the central processing unit
Published in Joseph D. Dumas, Computer Architecture, 2016
Figure 3.38 shows the basic layout of a simple hardwired control unit. The instruction register (IR) is used to hold the bits of the currently executing machine instruction. Its outputs, particularly those that correspond to the op code bits, are connected to a decoder that generates a unique output corresponding to that instruction. This is how the machine knows what it is supposed to be doing. The CPU’s clock signal is connected to a counter (referred to as the control step counter); by decoding the current counter state, the control unit is aware of which step in the execution of the current instruction it is now performing. These decoder outputs, possibly in addition to other machine state information, are input to a block of AND/OR combinational logic (in the early days, implemented as “random” logic; in modern designs, as a programmable logic array) that generates all the required control signals.
The BEMS central station
Published in G.J. Levermore, Building Energy Management Systems, 2013
The microprocessor, the chip at the heart of all BEMSs outstations and the central station, only operates with digital signals. These signals form a low-level programming language, or machine language, which consists of binary numbers representing instructions for the microprocessor as well as data and memory addresses. Machine language instructions consist of two parts: the operation code, or opcode, is the operation to be performed, and the operand is the number or address on which the operation is to be performed. Most CPU instructions can be summarized as fetch and execute operations. There are surprisingly few instructions for a CPU. The Intel 8088, used on many of the early IBM PCs, has a set of about 100 basic instructions. The instruction to add is simply 00000101.
O
Published in Philip A. Laplante, Comprehensive Dictionary of Electrical Engineering, 2018
opcode a part of an assembly language instruction that represents an operation to be performed by the processor. Opcode was formed from the contraction of "operational" and "code." open circuit impedance the impedance into an N-port device when the remaining ports are terminated in open circuits. open drip-proof (ODP) pertaining to a ventilated machine whose openings are constructed to prevent drops of liquid or solid particles falling on the machines at an angle less than 15 from the vertical from entering the machine either directly or by rolling along a horizontal or inwardly inclined surface of the machine. open kinematic chain a chain that consists of one sequence of links connecting two ends of the chain. open loop gain See open-loop gain.
Machine learning techniques to predict sensitive patterns to fault attack in the Java Card application
Published in Journal of Experimental & Theoretical Artificial Intelligence, 2018
Yahiaoui Chahrazed, Lanet Jean-Louis, Mezghiche Mohamed, Tamine Karim
When an attack changes an opcode byte, then it may change the number of following bytes used as operands: a shift in the instruction flow occurs which may remain shifted until it eventually recovers its normal flow. Let us consider an example of an attack targeting an instruction with one operand which is replaced by an instruction without operand. The operand of the impacted instruction is viewed as an opcode and the instruction flow is shifted until possibly returning to the original instruction flow. The sequence of instructions from the fault injected until the recovery of the initial code is called a mutant. The original code that has mutated is the sensitive pattern code. In our example, the mutant code is the sequence of instructions from instruction 07 to instruction 10 in Table 2, and the pattern code is the sequence of instructions from instruction 07 to instruction 10 in Table 1.