China
Africa
Explore chapters and articles related to this topic
MOSFET Design and Its Optimization for Low-Power Applications
Published in Suman Lata Tripathi, Parvej Ahmad Alvi, Umashankar Subramaniam, Electrical and Electronic Devices, Circuits and Materials, 2021
P. Vimala, M. Karthigai Pandian, T. S. Arun Samuel
In a conventional IC, the active components are implemented as a thin layer of surface and a depletion layer of a p–n junction as shown in Figure 1.5a separates them from the silicon body. Temperature changes tend to increase the junction leakage current, and this reduces the reliable nature of the device. Increased leakage current and huge dissipation of power in the form of surface heat due to increased temperatures will critically restrict the performance of microcircuits. The silicon-on-insulator (SOI) technology has become a very attractive alternative to replace the bulk CMOS technology since the traditional bulk MOSFET transistor downscaling process exceeded the limits of miniaturization and manufacturing of devices. Because of their cost relative to other semiconductors, silicon wafers are still retained as the starting point in the fabrication of ICs. SOI technology uses a thin layer of semiconductor silicon, which is separated from a sheet of silicon substrate by a slightly thicker SiO2 layer, as shown in Figure 1.5b. Dielectric isolation of components can be achieved using the SOI methodology and in combination with lateral isolation, it can get rid of latch-up failures and parasitic capacitances are also avoided.
Epitaxy
Published in Kumar Shubham, Ankaj Gupta, Integrated Circuit Fabrication, 2021
Epitaxial growth not only can introduce defects but also propagate defects. If these defects are in the active region of the wafer where the transistors are fabricated, they will often lead to device failures. These failures can be caused directly by electronic states associated with the defects, which lead to excessive leakage. Failures may also be less direct. The crystal perfection is frequently inferior of an epitaxial layer and can never exceeds that of the substrate. The crystal perfection is a function of the epitaxial process and the properties of the substrate wafer itself. During processing, the defects may trap other impurities in the wafer that contribute to these electronic states. The defects may also lead to excessive impurity diffusion during processing, which changes the physical device structure.
Design of 7T SRAM Cell Using FinFET Technology
Published in Suman Lata Tripathi, Sobhit Saxena, Sushanta Kumar Mohapatra, Advanced VLSI Design and Testability Issues, 2020
T. Santosh Kumar, Suman Lata Tripathi
In deep submicron CMOS technology, leakage current becomes an enormous problem. In semiconductor devices, leakage is a quantum occurrence where mobile charge carriers (electrons or holes) tunnel through an insulating region. As the thickness of the insulating region decreases, leakage increases exponentially. Junction tunneling leakage can also take place across between heavily doped P-type and N-type semiconductor junctions. Carriers can also leak between source and drain terminals of a metal oxide semiconductor (MOS) transistor, other than tunneling via the gate insulators or junctions. This is identified as subthreshold conduction. Although the primary source of leakage occurs inside transistors, electrons can also leak between the interconnects. Leakage increases power consumption and, if sufficiently large, can cause complete circuit failure. The three major components of leakage current such as subthreshold leakage, gate leakage, and junction tunneling leakage have been explained as follows.
Design of energy efficient domino logic circuit using lector technique
Published in International Journal of Electronics, 2022
Km Anjali Verma, Manish Kumar, Saurabh Kumar, R. K. Chauhan
This manuscript represents a modification in the existing technique of foot-driven stack transistor. The Lector technique (Hanchate & Ranganathan, 2004) and an NMOS transistor are used in the modified circuit, which is driven by a dynamic node. The major source of power consumption in digital circuits is leakage current, short circuit current, and charging-discharging of load capacitance. The major reason for leakage is subthreshold leakage and gate oxide leakage. The proposed lector-based domino logic circuit can effectively be used to reduce gate oxide and subthreshold leakage current. Therefore, the proposed circuit can be used for battery-powered applications and can also be used for wide fan-in circuits (Gupta & Khare, 2013). The modified domino circuits have low power dissipation, delay, high noise margin, and better power delay product.
Gaussian distribution model for gate-to-channel capacitance for carbon nanotube field-effect transistor
Published in International Journal of Electronics, 2019
Atheer M. Al-Shaggah, Abdoul M. Rjoub, Mohammed A. Khasawneh
This process of component size shrinkage is rather vital as components become packed more densely than ever, where the size of the chips is fairly small (Ebrahimi & Keshavarzian, 2013). Several challenges due to MOSFET scaling to nanoscale manifest themselves in various ways, with current leakage being the most prominent as it dissipates relatively significant energy proportions, confuses nearby transistors and corrupts electric signals (Sharifi et al., 2015). Leakage current is caused by the Short Channel Effect and adversely affects the overall behaviour of a transistor. Therefore, it accounts for the major portion of unwanted rate of current flow through the three main parts of MOSFET (gate, drain and source). Many types of leakage currents at the nanoscale were investigated in recent years categorising them into three major types including subthreshold leakage (Isub), Gate leakage (Ig) and Band-to-Band Tunneling (IBTBT) (Mehrabani & Eshghi, 2016). This type of categorization is in accordance with the reverse bias effect and the reduction of the oxide thickness to levels below 4 nm.
A novel design of full adder cell for VLSI applications
Published in International Journal of Electronics, 2023
Onteru Anjaneyulu, C. V. Krishna Reddy
The leakage power is measured in idle-state of the circuit means, while doing no computation (there is no utilisation of the circuit at that moment but in ON-state). Generally, leakage current is the integration of different components such as subthreshold leakage when the device is operating below threshold voltage and gate leakage current due to thinner gate oxide at sub-micron technological nodes. The leakage power is dominative at sub-65 nm node due to threshold voltage roll-off and gate oxide thickness is lower well below 1.5 nm. Leakage power dissipation of different adders at room temperature and supply voltage of 1 V is shown in Figure 14. It can be observed that the leakage power is higher for NMNFA and lower HCFA.