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An Efficient System Design for a 32 Bit Sum-Product Operator in Modified Booth form Using Fusion Technique
Published in T. Kishore Kumar, Ravi Kumar Jatoth, V. V. Mani, Electronics and Communications Engineering, 2019
The theoretical generation and practical observation of both existing and proposed systems in terms of occupied area and delay in critical path are shown in Figure 14.9 and below tables. This analysis of circuits is based on the unit gate model. More specifically, for the quantitative comparisons, the two-input primitive gates (NAND, AND, NOR, OR) count as one gate equivalent for both area and delay, whereas the two-input XOR, XNOR gates count as two gate equivalents.7 The area of FA and an HA is 7 and 3 gate equivalents, respectively. The delays of the sum and carry outputs of an FA are 4 and 3 gate equivalents, respectively, while those of an HA are 2 and 1.8 All the aforementioned information is summarized in Table 14.2.
Design and Evaluation of Multipliers Using Simulated Annealing and Partitioning Approach
Published in IETE Journal of Education, 2023
Pavitra Y.J., Jamuna S., Manikandan J.
Espresso [42] and ABC [43] are conventional circuit synthesis tools that are well accepted in the field of optimization and majorly used as the baseline for metaheuristic design comparisons. Binary decision diagrams (BDD) are widely used in commercial tools for the verification and synthesis of circuits which provides a good compromise between conciseness of representation and efficiency of manipulation [44]. PolyBDD, an extension of BDD to determine elementary polymorphic functions, is proposed in [22] for circuit optimization because of its low-cost implementation. CGP is widely used in the literature for circuit optimization. The resource count for a 4-bit multiplier using the proposed algorithm presented in Table 2 is used as a baseline to compare with above-mentioned techniques reported in the literature and the comparative analysis/results are presented in Table 3. The 2-input logic gate equivalent for resource types PD2-PD4 reported in Table 2 is computed as per the details provided in Table 4 and is reported in Table 3. It can be observed from Table 3 that 3.67-95.75% of resources are saved and 100% SR is achieved using the proposed partitioning approach and SA. Table 3 reveals that PD1 outperforms all designs (PD2–PD4) and techniques (Espresso, BDD, ABC, PolyBDD, CGP) reported in the literature for a 4-bit multiplier. For better visualization of Table 3, the bar chart of resources consumed in terms of 2-input gates is shown in Figure 6.
Parameter extraction and modelling of the MOS transistor by an equivalent resistance
Published in Mathematical and Computer Modelling of Dynamical Systems, 2021
Sherif M. Sharroush, Yasser S. Abdalla
The second method for determining CG depends on applying a dc voltage source, VGG, in series with a resistance, R, on the gate terminal of the MOSFET transistor with the other terminals grounded as shown in Figure 12. If the voltage source is connected directly to the gate terminal, the gate voltage will be equal to VGG at all cases and there will be no way of discovering the gate equivalent circuit. If the gate contains a capacitance only, the steady-state gate voltage, VG, will be constant irrespective of the value of R. However, this is not the case; rather, VG decreases with increasing R as indicated in Figure 13. So, the gate contains a resistance, RG, as concluded in the illustration of the first method and illustrated in Figure 14. In order to avoid the effect of the voltage dependence of RG on vG, relatively small values of R are adopted so that the steady-state gate voltage will be constant at VGG. As a result, the instantaneous gate voltage is described by the following relationship: