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Fundamentals of TFETs and Their Applications
Published in Balwinder Raj, Ashish Raman, Nanoscale Semiconductors, 2023
V. Ramakrishna, A. Krishna Kumar
Tunneling occurs at the source–channel junction while the system is in ON mode; thus, the source gate is referred to as the tunneling gate. The auxiliary gate is the gate closest to the drain. Sidewall spacer methods can be used to build the DMG frame. Figure 2.8 depicts a cross section of a DMG TFET. The source and drain are made up of highly doped p-type and n-type regions, respectively. A substantially doped n-type layer makes up the intermediate channel area. The gate dielectric is silicon dioxide (SiO2). The gate is made up of two materials, M1 and M2, and has L1 and L2 gate lengths as well as m1 and m2 work functions. The device is classified as an n-type TFET or a p-type TFET depending on whether a positive or a negative voltage is applied to the gate terminal. The transistor functions as an n-TFET when a positive gate voltage is supplied and as a p-TFET when a negative gate voltage is applied [34].
Tunnel FET: Working, Structure, and Modeling
Published in Niladri Pratap Maity, Reshmi Maity, Srimanta Baishya, High-K Gate Dielectric Materials, 2020
where the parameter λ has several different names, including screening length, natural length, or Debye length, and refers to the spatial extent of the electric field, or the length over which an electric charge has an influence before being screened out by the opposite charges around it (Streetman and Banerjee, 2000). It can be expressed in terms of the dielectric constants and thicknesses of the gate dielectric and semiconductor body of a device, and depends upon gate geometry. There are four important conditions in order for band-to-band tunneling to take place: available states to tunnel from, available states to tunnel to, an energy barrier that is sufficiently narrow for tunneling to take place, and conservation of momentum (Sze, 1981). This equation shows decreasing oxide thickness (tox), increasing oxide constant (εox), and reducing bandgap (Eg), enhance the performance of the device. From the above equation, it can be seen that the band-to-band tunneling current, IB2B increases exponential with an increase in VGS as T(E) increases. Boucart and Ionescu (Boucart and Ionescu, 2007) have proposed the use of high-k materials as the gate dielectric high εox in eq 8.1 in order to increase ON current (Ion). In this work, Ion enhancement has been done by modulating the bandgap (Eg).
Process Variability and Reliability of Nano-Scale CMOS Analog Circuits
Published in Soumya Pandit, Chittaranjan Mandal, Amit Patra, Nano-Scale CMOS Analog Circuits, 2018
Soumya Pandit, Chittaranjan Mandal, Amit Patra
The time dependent dielectric breakdown phenomenon in gate oxides is an irreversible reliability phenomenon that results in a sudden discontinuous increase in the conductance of the gate oxide at the point of breakdown, as a result of which the current through the gate insulator increases significantly [192]. The breakdown of a gate dielectric insulator occurs due to the application of a high electric field (such as 5MV/cm) over a period of time. There are several theories explaining the TDDB phenomenon. Among them the two most important theories are the anode hole injection theory and the percolation theory. However, before going into the details about the TDDB phenomenon in scaled MOS transistors it is important to understand the electrostatics of any dielectric medium.
Electrostatically Doped Schottky barrier tunnel field effect transistor
Published in International Journal of Electronics Letters, 2022
Harendra Kumar, Sangeeta Singh, Kumari Nibha Priyadarshani
The cross-sectional view of the device structure for ED-SB-TFET is shown in the Figure 1. Here, we have considered the gate length as 10 nm and the spacer is 3 nm to isolate the extended metal at the drain side. This 3-nm Hf metal spreads over the channel at the drain side to increase the conduction current in ON state and it is also helpful for controlling the carriers in the OFF state thereby improves the leakage performance. The device has a drain-side electrode contact extension to enhance the ratio. We have employed high-K material (Hf with dielectric constant as 21) as a gate dielectric as well as a spacer. Here, SB-TFETs have its source replaced with p-type (PtSi) silicide, as opposed to highly doped silicon regions. As the schottky junction offers low parasitics, superior scaling properties, easy fabrication and lower thermal budget. Using the silicide in the source lowers the resistance and it also realises automatically a highly abrupt change in concentration in the channel. The silicidation process needs low temperature fabrication steps it enables its compatibility with high-K dielectrics and the metal gate stack. It also eliminates the latch-up and parasitic bipolar action. The detailed simulation parameters considered for the device simulation are tabulated in Table 1.
Impact of Non-Uniform Doping on the Reliability of Double Gate JunctionLess Transistor: A Numerical Investigation
Published in IETE Technical Review, 2022
Vandana Kumari, Mridula Gupta, Manoj Saxena
In Figure 9(a), gate current has been plotted for five different doping profiles (description has been mentioned in Table 1). Device having Case E and A type doping profile have higher leakage current compared to other doping profiles due to the higher vertical electric field. Effective doping inside the channel for Case A and Case D are approximately the same, but the leakage current for case D is slightly lower than case A. This is because for Case A, doping at the surface is 1018 cm−3 (N1) and 1019 cm−3 (N3) however, for Case D, it is 1018 cm−3 at both upper and lower surface (N1= N3) which leads to slightly lower vertical electric field and hence lower gate leakage current. Case E which shows a higher Ion/Ioff ratio as discussed in the previous section. But similar to BTBT current, device having Case E type doping profile have also exhibited larger gate leakage current than Case C and B because of higher vertical electric field (resulted from lower doping concentration). Case F (having uniform doping (1019 cm−3)) has leakage current similar to Case C. With the reduction in source drain extension length from 20 nm to 0 nm in Figure 9(b) for Case A doping, ungated region which is heavily doped becomes zero and thereby leading to higher electric field. The enhancement in gate leakage current at zero source/drain extension length is around 3 orders as shown in Figure 9(b). In Figure 9(c) variation of gate leakage current with oxide permittivity has been plotted for Case A doping profile. Higher oxide permittivity leads to the enhancement in gate leakage current due to the enhancement in vertical electric field. The introduction of high-k gate dielectric leads to reduction in effective oxide thickness which is also responsible for the enhancement of gate leakage current.
Impact of cation compositions on the performance of thin-film transistors with amorphous indium gallium zinc oxide grown through atomic layer deposition
Published in Journal of Information Display, 2019
Min Hoe Cho, Min Jae Kim, Hyunjoo Seul, Pil Sang Yun, Jong Uk Bae, Kwon-Shik Park, Jae Kyeong Jeong
Bottom-gate, top-contact-structure a-IGZO TFTs were fabricated on a p+-Si substrate. A heavily doped, p-type Si wafer was used as the gate electrode, and a thermally oxidized 100-nm-thick SiO2 layer was used as the gate dielectric. 13-nm-thick a-IGZO active layers were deposited in a traveling-wave-type ALD apparatus (CN1 Co., Ltd., South Korea). The proposed source canisters are bypass-type: metal precursors were injected directly into the source line, and 50 standard cubic centimeter per minute (sccm) N2 gas was used as the carrier gas for the precursor delivery. The N2 gas flow rate was controlled by a mass flow controller. The canister containing the In precursor was maintained at 80°C to provide sufficient vapor pressure and dose, while the canisters containing the Ga and Zn precursors were kept at room temperature because they have sufficient vapor pressure at room temperature. O3 was used as a reactant. A 970 sccm O2-30 sccm N2 gas mixture was introduced into the O3 generator, which produces O3 gas at a 250 g/m3 concentration. An a-IGZO active layer was grown in one cycle, which consists of several sequential steps in a sequence of In2O3, ZnO, and Ga2O3 subcycles. By adjusting the number of subcycles of each binary metal oxide, a-IGZO layers with different cation compositions were obtained. A rather long purge time (10 s for each metal precursor and O3 purge) was adopted to prevent the mixing of the precursors and the reactant. The substrate temperature was set at 250°C, at which simultaneous self-limiting behaviors of the In2O3, Ga2O3, and ZnO films in terms of the substrate temperature were observed. The a-IGZO active layer was patterned via photolithography and wet etching. After that, post-deposition annealing (PDA) was performed in the air for 1 h, at 200°C, for the a-IGZO active layer. An indium tin oxide (ITO) film was deposited as a source/drain (S/D) electrode via DC magnetron sputtering, and was patterned through the lift-off method. The channel width (W) and length (L) of the a-IGZO TFTs were 10 and 50 µm, respectively. The completed devices were subjected to contact annealing in the air for 1 h, at 250°C.