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Contactless Angle Detection in Automotive, Consumer, and Industrial Applications
Published in Kevin Yallup, Krzysztof Iniewski, Technologies for Smart Sensors and Sensor Fusion, 2017
Antonio J. López-Martýn, Alfonso Carlosena
A related approach consists in the implementation of the LUT by means of combinational logic. The input word is applied to the combinational logic, and the linearized word appears at the output. This solution does not require the utilization of a physical memory, so it is very convenient in low-cost ICs, where the need for an internal ROM may significantly increase the price. This approach is particularly effective when the table size is not very large, because in this case, the silicon area occupied by the combinational logic tends to be much lower than the size required for a ROM memory. Again a trade-off between silicon area and processing time appears, as gate count in the combinational logic can be decreased if more logic gate stages are allowed, which increases delay. However, the combinational circuit cannot be reconfigured, so it cannot be rearranged to linearize other types of nonlinear functions. Both in the LUT and in this approach, significant area savings can be achieved with minor extra processing if the table or combinational logic provides the difference between the output word and the corresponding input word. Such procedure corresponds to the storage of the difference between the nonlinear response and a straight line instead of the nonlinear response itself. In the GMR sensor bridge employed, it would correspond to the difference between the arcsin(x) function (in the required angular range) and a linear function. This method is specially useful for weak nonlinearities.
Mapping Boolean Expressions
Published in Eugene D. Fabricius, Modern Digital Design and Switching Theory, 2017
In general, the lower the gate count, the lower the power dissipation, and the smaller the number of gates a signal must pass through, the faster the circuit. While the minterm and maxterm expansions of any function are unique, the implementation of a minterm or maxterm expansion is in general very wasteful of gates, and simplified SOP and POS solutions are needed.
Asynchronous Wrapper-Based Low-Power GALS Structural QDMA
Published in IETE Journal of Research, 2022
B.K. Vinay, S. Pushpa Mala, S. Deekshitha
Response by control logic, storage elements to transition on signal is more complex. Thus, a two-phase bundled data protocol is a chosen approach in a high-speed system with unconditional data flow. Besides, there is a significant reduction in dynamic power dissipation as there are reduced transitions in two-phase handshake protocol and clock gating techniques. The improvement in the reduced power dissipation and better throughout attainment is achieved at the cost of a marginal increase in average gate count.