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Case Studies
Published in Lambrechts Wynand, Sinha Saurabh, Abdallah Jassem, Prinsloo Jaco, Extending Moore’s Law through Advanced Semiconductor Design and Processing Techniques, 2018
Lambrechts Wynand, Sinha Saurabh
Its latest offering, announced in 2017 and planned to be mass-produced in 2018, is the Volta line of GPUs, a processing unit based on a 12 nm FinFET technology node, housing 21 billion transistors in its main processing core on a die size of 815 mm2 (Nvidia 2017). Its predecessor, the Pascal line of GPUs, was built on a 14 nm technology and contained 15 billion transistors on a die size of 610 mm2 on its primary processing core. Huang additionally said, during this keynote address, that the Volta GPU is at the limits of photolithography, therefore acknowledging that this process step (photolithography) is the primary challenge to adhering to Moore’s law. The Volta line of GPUs has a redesigned microprocessor architecture with respect to the Pascal line, and is able to operate 50% more efficiently than its predecessor. In addition, these GPUs implement high bandwidth memory (HBM) for their video RAM (VRAM), as opposed to the traditional, albeit less costly, double data rate (DDR) memory – currently type 5, GDDR5 (Nvidia 2017). HBM uses vertically stacked dynamic RAM (DRAM) memory chips interconnected by through-silicon vias, shortening the path between individual memory chips, effectively reducing power consumption, reducing the required area and allowing for higher bandwidth at lower clock speeds.
Challenges and Future Directions of 3D Physical Design
Published in Aida Todri-Sanial, Chuan Seng Tan, Krzysztof Iniewski, Physical Design for 3D Integrated Circuits, 2017
Johann Knechtel, Jens Lienig, Cliff C.N. Sze
For 3D memory integration, the industry has passed the prototyping stage, and is recently approaching high-volume manufacturing. For example, since end of 2014, SK Hynix offers HBM modules [120]. With 128 GB/s, these modules provide approx. 4.5× the bandwidth of state-of-the art GDDR5 modules. Alok Gupta, PE at Nvidia, presented at the 3D ASIP 2014 conference [5] a GPU-on-interposer system comprising four HBM modules and achieving a bandwidth of 1 TB/s. Another example are the efforts of Samsung: since 2013, the company is mass-producing so-called vertical-NAND (V-NAND) memory [114]. Here, as the name suggests, the transistors are vertically arranged, that is, the gate and insulator are circularly wrapped around the channel. These transistors are then repeatedly processed onto many stacked layers. With this dedicated design, achieving integration density in the vertical dimension instead of traditionally in the plane, wider bit lines and the deployment of “old” but much more reliable process nodes (e.g., 30 nm) are feasible. These two measures effectively reduce cell-to-cell interferences and small-scale patterning issues, which are major concerns for modern memory technology.
Augmented reality and mixed reality behavior navigation system for telexistence remote assistance
Published in Advanced Robotics, 2021
Eimei Oyama, Kohei Tokoi, Ryo Suzuki, Sousuke Nakamura, Naoji Shiroma, Norifumi Watanabe, Arvin Agah, Hiroyuki Okada, Takashi Omori
The prototype system comprised (1) a laptop computer (Razer Blade 14, with the 64-bit Windows 10 Professional, Intel Core i7-7700HQ (2.80 GHz) CPU, and 16 GB of RAM installed, and an NVIDIA GeForce GTX 1060 with 6 GB of GDDR5 VRAM), (2) an Oculus Rift CV1 VR HMD, and (3) a single stereo camera (an OVRvision Pro by Wizapply Team (Shinobiya.com Co.,Ltd)) for the non-expert, as illustrated in Figure 6. A 3D motion sensor system included in the VR HMD was used for the VR display. The utilized camera had a viewing angle of 115° horizontal by 105° vertical, an image resolution of 960 × 950, and a frame rate of 60 Hz. The prototype system for the expert comprised (1) a laptop computer (Razer Blade 15, with Windows 10 Professional (64 bit), Intel Core i7-8750H (2.20 GHz) with 16 GB RAM, and NVIDIA GeForce GTX 1060, with Max-Q and 6 GB of GDDR5 VRAM) and (2) an HMD with Leap Motion, as represented in Figure 7. In the experiment described Section 5 below, the expert's and the non-expert’s computers were connected via an IEEE 802.11n wireless LAN router, with a maximum speed of 800 bits per second (bps).
Multi-product continuous plant scheduling: combination of decomposition, genetic algorithm, and constructive heuristic
Published in International Journal of Production Research, 2020
Pavel Borisovsky, Anton Eremeev, Josef Kallrath
The DP algorithm was implemented in C using the NVIDIA CUDA library (https://developer.nvidia.com/cuda-zone). The GA was implemented in C++. For solving the LP-subproblems (12)–(15) in the GA, a dual simplex algorithm from QSOPT library (http://www.math.uwaterloo.ca/∼bico/qsopt/) was used. The model (1)–(11) was implemented in GAMS (http://www.gams.com) with CPLEX 12.3 as a MILP solver. The experiments were run on PC with AMD Phenom 2.8 Mhz processor and 4 Gb RAM under MS Windows XP (32 bit) with GPU device GeForce GTS 450, 1Gb GDDR5 RAM.
Accuracy evaluation of the semi-automatic 3D modeling for historical building information models
Published in International Journal of Architectural Heritage, 2018
Daniel Antón, Benachir Medjdoub, Raid Shrahily, Juan Moyano
The duration of these automatic tasks depends on the 3D mesh multiple factors (i.e., file size, and original and preferred number of points and vertexes) and hardware. The system used for this research was an average portable computer with the following main specifications: 4-core microprocessor at 3.3 GHz maximum; 16 GB DDRIII RAM memory at 1,600 MHz; and a PCI Express 2.0 graphic card with 336 GPU cores, 598 MHz graphics clock, and 3 GB 192-bit GDDR5 memory at 1,500 MHz with bandwidth of 72 GB per second. Therefore, it can be stated that this proposal does not need powerful hardware to be carried out.