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Force-System Resultants and Equilibrium
Published in Richard C. Dorf, The Engineering Handbook, 2018
The central processing unit (CPU) executes sequences of instructions and operands, which are fetched by the program control unit (PCU), executed by the data processing unit (DPU), and, then, placed in memory. In particular, caches (high speed memory where data is copied when it is retrieved from the random access memory improving the overall performance by reducing the average memory access time) are used. The instructions and data form instruction and data streams which flow to and from the processor. The CPU may have two or more processors and coprocessors with various execution units and multi-level instruction and data caches. These processors can share or have their own caches. The CPU datapath contains nanoICs to perform arithmetic and logical operations on words such as fixed- or floating-point numbers. The CPU design involves the trade-offs analysis between the hardware, speed, and affordability. The CPU is usually partitioned on the control and datapath units, and the control unit selects and sequence the data-processing operations. The core interface unit is a switch that can be implemented as autonomous cache controllers operating concurrently and feeding the specified number (32,64, or 128) of bytes of data per cycle. This core interface unit connects all controllers to the data or instruction caches of processors. Additionally, the core interface unit accepts and sequences information from the processors. A control unit is responsible for controlling data flow between controllers that regulate the in and out information flows. There is the interface to input/output devices. On-chip debug, error detection, sequencing logic, self-test, monitoring, and other units must be integrated to control a pipelined nanocomputer. The computer performance depends on the architecture and hardware components (which are discussed in this Chapter). Figure 148.10 illustrates the possible nanocomputer organization
Design of Molecular Integrated Circuits
Published in Sergey Edward Lyshevski, Molecular Electronics, Circuits, and Processing Platforms, 2018
Advanced computer architectures (beyond von Neumann architecture) can be devised and implemented to guarantee superior processing, reconfigurability, robustness, networking, and so forth. In the von Neumann computer architecture, the CPU executes sequences of instructions and operands, which are fetched by the program control unit (PCU), executed by the data processing unit (DPU), and then placed in the memory. Caches (high-speed memory in which data is copied when it is retrieved from the RAM, improving the overall performance by reducing the average memory access time) are used. The CPU may have more than one processors and coprocessors with various execution units and multilevel instruction and data caches. These processors can share or have their own caches. The datapath contains ICs to perform arithmetic and logical operations on words such as fixed or floating-point numbers. The CPU design involves the trade-off between the hardware/software requirements, performance, and affordability. The CPU is usually partitioned on the control and datapath units. The control unit selects and sequences the data processing operations. The core interface unit is a switch that can be implemented as autonomous cache controllers operating concurrently and feeding the specified number (64 or 128) of bytes of data per cycle. This core interface unit connects all controllers to the data or instruction caches of processors. Additionally, the core interface unit accepts and sequences information from the processors. A control unit is responsible for controlling data flow between controllers that regulate the in and out information flows. The interface is accomplished by means of input/output devices and units. On-chip debuging, error detection, sequencing logic, selftest, monitoring, and other units must be integrated to control a pipelined computer. The computer performance depends on the architecture, organization, and hardware components.Figure 4.11. illustrates the conventional computer architecture.
Commercial VLSI RISC
Published in S.B. Furber, VLSI Risc Architecture and Organization, 2017
them into the decoded instruction cache. The execution unit processes the instructions and modifies user data structures accordingly. There are two unusual consequences of this independent prefetching and decoding activity. Firstly, the prefetcher can see branches coming, and use the hint bit to determine whether the branch is likely to be taken. It can
A Bio-Inspired, Self-Healing, Resilient Architecture for Digital Instrumentation and Control Systems and Embedded Devices
Published in Nuclear Technology, 2018
Shawkat S. Khairullah, Carl R. Elks
In BioSymPLe each one of the three cells—B cell, T cell, and stem cell—has a similar internal structure, which is shown in Fig. 4. However, their functionalities are different and are based on the genetic codes stored in the configuration memory. The basic structure of the cell is comprised of two partitions: data flow and control flow. Data flow includes the data path for the adaptive functional block (AFB) unit, I/O routing direct unit, and I/O routing diagonal unit to make each cell capable of being connected to its neighboring cells from north, south, east, and west. The control flow embeds an address generation unit to store the address of the cell, a configuration memory that stores the next address of each cell and the genetic codes that configure both the execution unit and the two routing units, and a fault confinement unit to disconnect the faulty cell from its neighboring cells in case a permanent fault occurs inside the 1131 data path or the LUT data path.
Hydraulic-pressure-following control of an electronic hydraulic brake system based on a fuzzy proportional and integral controller
Published in Engineering Applications of Computational Fluid Mechanics, 2020
Qiping Chen, Hao Shao, Yu Liu, Yuan Xiao, Ning Wang, Qiang Shu
The EHB system comprises the pedal unit, the pressure building unit, the brake execution unit and the control unit. The EHB system working process is described as follows (Yang & Han, 2017). The pedal unit connected with the brake pedal provides the input signal of brake pedal displacement to the control unit. Figure 1 indicates that the pressure building unit is a secondary mechanical transmission mechanism driven by a motor. The brake execution unit contains the brake master cylinder, the brake pipeline and the brake wheel cylinder.