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Digital Logic Circuit Families
Published in Nassir H. Sabah, Electronics, 2017
In one form of domino logic, also known as NP Domino logic or NORA CMOS logic, dynamic logic gates are alternated between those using PDNs and PUNs, with an inverted CK applied to the gates having PUNs. Figure 13.4.5 illustrates two inverters cascaded in this manner. When CK is low, CK¯ is high, CL1 is precharged to VDD, whereas CL is “precharged” by QPR2 by discharging it to 0. During the evaluate phase, CK is high and CK¯is low. If A is high, CL1 discharges, pulling O1 low. As the voltage of O1 falls, Q2 is turned on, and with QEV2 on, CL charges to VDD, making O high. If A is low, CL1 remains high, Q2 is off, and O remains low.
Low-Power Very Fast Dynamic Logic Circuits
Published in Christian Piguet, Low-Power CMOS Circuits, 2018
All the preceding circuits are aiming at a high throughput regardless of the latency or the number of operating clock cycles for a final output. In many applications, however, the decision has to be made in one clock cycle. A technique named clock-and-data precharged dynamic (CDPD) circuit technique may offer an alternative for a fast one-clock-cycle decision and in the same time reduce the power consumption [14]. Domino logic is often used for logic calculations with a large depth as the logic parts can be distributed along the domino chain and are all in nMOS. As illustrated in Figure 8.15(a), however, an inverter has to be placed between two precharged stages to prevent an erroneous high-output to the next stage at the beginning of evaluation. Moreover, charge sharing may occur between the output node and the intermediate nodes so extra precharging transistors have to be used. As illustrated in Figure 8.15(b), all contents in the dashed line box can be replaced by only three transistors in CDPD technique, and no clocked transistor is contained in it. This CDPD block is named an H/L (high-to-low) stage in which the output is precharged to low by a high data input, and the NOR function is simply fulfilled by the two p-transistors. An H/L stage can be followed by an L/H (low-to-high) stage in which the output is precharged to high by a low data input. An n-type CDPD chain can be formed by the original domino precharged stages along with the H/L and L/H stages in between, as illustrated in Figure 8.16(a). It needs an odd number of CDPD stages between two domino precharged stages, and an even number of CDPD stages between a domino stage and an output latch.
Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology
Published in IETE Journal of Research, 2023
Domino logic is a clocked logic family which means that there is a clock in every logic gate. The continuous switching of clock in domino logic design leads to the higher power dissipation [4]. There are various domino logic topologies with modification in the keeper circuit to tolerate the device process parameters [5]. A variable strength keeper technique in [6] was design to chieve robust, high-speed, and low-leakage dynamic logic gates with carbon nanotube transistors. Low leakage domino logic is also design in [7] using carbon nanotube field effect transistor (CNTFET). Previous domino logic techniques maintain clock at high state during standby mode in order to reduce the static power dissipation. Here, we will propose a domino logic using clock gating technique and revised keeper circuitry using 16 nm CMOS technology. blueThis work have been inspired from the work done in [8]. In [8], a modified keeper consisting of both PMOS and NMOS transistors are used to reduce the power consumption of CMOS domino logic. This work uses the keeper which consists of only PMOS transistors with clock gating technique.
Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style
Published in International Journal of Electronics, 2020
A. Anita Angeline, V.S. Kanchana Bhaaskaran
Domino logic circuits are widely in use due to their reduced transistor count, high-speed performance and reduced logical effort (Ding & Mazumder, 2004). Realisation of wide fan-in gates using domino logic circuit style is normally preferred as in the Pull-Up Network (PUN); they evade stacking of transistors and are extensively used in design of Static Random Access Memory (SRAM) pre-decoders, tag comparators and programmable encoders (Asyaei & Ebrahimi, 2018; Nasserian, Kafi-Kangi, Maymandi-Nejad, & Moradi, 2016; Peiravi & Asyaei, 2012a). The domino logic circuit design with reduced transistor count and the evaluation being performed only by N-type Metal Oxide Semiconductor (NMOS) transistors makes it a preferable circuit style compared to static Complementary Metal Oxide Semiconductonductor (CMOS) circuit in terms of chip area and speed performance. However, it offers low noise gain margin due to leakage current and charge sharing which occur in the internal nodes. In addition, the dynamic power consumption is increased because of redundant switching at output node for every pre-charge operation, even for consecutive identical inputs.
Design of energy efficient domino logic circuit using lector technique
Published in International Journal of Electronics, 2022
Km Anjali Verma, Manish Kumar, Saurabh Kumar, R. K. Chauhan
Domino logic gates are widely used in modern digital VLSI circuits because of the high-speed processor and lower transistor count (Shah et al., 2016). Domino logic offers less noise margin due to charge-sharing at internal nodes and leakage current. When compared to a static CMOS logic gate, it requires less area (Peiravi & Asyaei, 2012). Domino logic circuit attains high speed and is highly sensitive to noise due to low noise margin. The speed of the domino increases when there is a reduction in threshold voltage. In domino logic gates, evaluation is performed by only the NMOS transistor, which makes it a preferable circuit design.