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Memory Organisation
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
Main memory (RAM) cell realization using dominant technologies in the form of Static RAM (SRAM) and Dynamic RAM (DRAM), and subsequent organisation of these cells in 2D arrays to form a full-fledged RAM chip have been described. Subsequent developments of DRAM with constant improvement in fabrication technology eventually made it possible to realize DDR, DDR1, DDR2, and also DDR3 to meet the ever increasing demand of main memory space and speed. Introduction of non-volatile ROM and its different variants located at the same level of RAM in the memory hierarchy have supplemented the primary memory support by way of providing different application activities. Still, the main memory space scarcity problem remains as the computing environment gradually changes, and this crisis has been ultimately mitigated by way of including a relatively larger virtual memory (a portion of the disk, but behaves like a primary memory) in the memory system as a standard feature. But, this requires an additional time-consuming hardware-supported mechanism built within the processor for translating the issued virtual-memory addresses to actual physical addresses (primary memory address) needed during run-time. As a result, the memory response time further increases that summarily degrades the existing overall system performance. To minimize this degradation in performance as well as to compensate the constantly increasing speed disparity between CPU and main memory due to relentless advancement of electronic technology, one or more intermediate faster, smaller, and comparatively costlier memories known as cache memory are injected in the memory system in between CPU and main memory to reduce the effective memory access time as experienced by the processor. Nowadays, almost all modern systems including more powerful modern microprocessors, not only use large size caches, but incorporates multi-level on-chip caches (L1, L2, and even L3) apart from using large off-chip cache on board. Splitting of caches and efficient use of them with effective balancing of other design parameters including appropriate mapping scheme have been able to substantially minimize the undesirable effects of memory latency. Caches, when used in multiple-processor architectures provide them enormous processing capabilities to handle many different classes of constantly emerging numerous application areas. But, at the same time, they invite a critical issue known as cache inconsistency or cache coherent problem. Appropriate mechanisms (mostly by means of hardware-based approach now a days) are thus employed to get rid of this serious problem to enjoy the ultimate benefit of cache usage. All these aspects as mentioned have been adequately addressed and described with respective figures to complete the discussion convincingly.
Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform
Published in International Journal of Electronics, 2019
Jai Gopal Pandey, Abhijit Karmakar
The architecture is compared with the established architectures of (Asari et al., 1999; Tian et al., 2003b). Further, the architecture has been wrapped with necessary interface logic so that it can be used as an IP core in the FPGA-SoC environment. Here, the core is interfaced with the processor local bus (PLB), and the embedded PowerPC processor (Xilinx, 2011) is utilized to control the frame acquisition process. The other side of the bus is used to communicate with the DDR2 memory, which is controlled by a multiport memory controller (MPMC). The communication is established with the native port interface (NPI). An embedded application of the core is demonstrated for image connected component labelling application. The real-time video is captured with an analogue PTZ camera. The RGB-to-grey conversion and image thresholding computations are implemented in the hardware, whereas the Stefano–Bugarelli algorithm (Stefano & Bulgarelli, 1999) for connected component analysis (CCA) is implemented in the PowerPC processor. The required IPs and configuration software are managed in an integrated fashion with the use of Xilinx platform studio design tool.