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Published in Philip A. Laplante, Comprehensive Dictionary of Electrical Engineering, 2018
DC block A circuit simulation component that behaves like a capacitor of infinite value. DC chopper a DC to DC converter that reduces the voltage level by delivering pulses of constant voltage to the load. The average output is equal to the input times the duty cycle of the switching element. DC circuit electrical networks in which the voltage polarity and directions of current flow remain fixed. Thus such networks contain direct currents as opposed to alternating currents, thereby giving rise to the term. DC current constant current with no variation over time. This can be considered in general terms as an alternating current (AC) with a frequency of variation of zero, or a zero frequency signal. For microwave systems, DC currents are provided by batteries or AC/DC converters required to "bias" transistors to a region of operation where they will either amplify, mix or frequency translate, or generate (oscillators) microwave energy. DC drain conductance for an FET device under DC bias, the slope of the output drain to source current (I DS ) versus output drain to source voltage (V DS ) for a fixed gate to source voltage (VG S ),
Reconfigurable grounds MIMO antenna with PIN diodes for 5G NR n3/n1/n40/n41/n77/n79 to X-bands
Published in International Journal of Electronics, 2023
Srinivasu Garikipati, Gayatri Tangirala, Manikya Krishna Chaitanya Durbhakula, Virendra Kumar Sharma
RF chokes are needed between PIN diodes and DC bias to achieve low impedance path to DC voltage thereby isolates RF and DC. Also a DC block capacitor is used to isolate the RF source and DC supply. For PIN diodes, a DC-RPS is used to supply −0.8 V for reverse bias condition (OFF state) or +0.8 V to attain the forward bias condition (ON state). The required bias lines are extended by connecting wires. The equivalent circuit model of the PIN diode for OFF state has a series inductance, L = 0.7 nH, a parallel combination of a high resistance, R1 = 5kΩ and capacitance, C = 0.21 pF, whereas the ON state has a series inductance, L = 0.7 nH and a series low resistance, R2 = 0.85 Ω. These values are chosen for lumped RLC model in HFSS simulation. To support the simulations two conductive pads of dimensions 0.8 × 0.8 mm2 are located on the ground plane. This complete setup is shown in Figure 1.
Board-Level Ku-Band Power Amplifier: Design and Challenges
Published in IETE Journal of Research, 2022
Hemant Kumar Singhal, Karun Rawat
In general, capacitors are used for DC blocking and inductors are used for DC feed-in PA circuits. The simplified two-port circuit model of capacitors is shown in Figure 1 [27]. C is the capacitance, CP, RS and LS represent the parallel capacitance, series resistance and series inductance, respectively. From Figure 1, one can observe that there are two resonance frequencies for capacitors: SRF and PRF. At SRF, the equivalent impedance between port-1 and port-2 is minimum, while at PRF, it is maximum. Below SRF, capacitors behave like DC block capacitor and above SRF, it behaves like DC block inductor. The capacitor may be used as an inductor above SRF. At PRF, the capacitor provides the highest transmission impedance and the capacitor is generally useless around PRF due to more insertion loss. Therefore, the capacitor must be used as a DC block below PRF and near to SRF [28]. At the time of selecting an inductor for DC feed, it is not enough to consider only required inductance. The designer should take into account that operating frequency must not be much higher than SRF of the inductor. Moreover, at Ku-band, DC feed inductors are rarely available and they introduce high parasitic to the circuit. Thus, it is preferable to realize DC feed network using a distributed line at higher frequencies.
A dual circular and linear polarized rectenna for RF energy harvesting at 0.9 and 1.8 GHz GSM bands
Published in Electromagnetics, 2021
Harvesting in dual wideband operation requires the use of a rectifier circuit operating in a dual wideband frequency. In our layout, as shown in Figure 4, a dual wideband matching network is accomplished and designed through the insertion two optimized coupled lines with one shorted end stub before each of the divider branches as described in Long Lin et al. (2017). Actually, it can produce impedance matching at two frequencies that can realize wideband matching at different bands. Each branch is designed to get the circuit matched around 0.9 and 1.8 GHz. As shown in Figure 4, capacitor C1 is part of the basic voltage doubler rectifier circuit that can be considered as a DC-block for preventing the DC power from returning back to the signal source. Meanwhile, capacitor C2 is used as a DC-pass filter to smooth waveform and store the energy of the output DC before the resistance load RL. The matching and rectifier circuits are simulated, analyzed, and optimized using Harmonic Balance (HB), Large Signal S-parameter (LSSP), and Momentum from Keysight ADS. In order to improve the accuracy, a spice model for the Schottky diodes of the Avago Technology is applied in the simulation (Non 2010). The chip capacitors in the design are also demonstrated by S-parameter files intended by Murata.