China
Africa
Explore chapters and articles related to this topic
Electronic circuit applications
Published in Joe Cieszynski, David Fox, Electronics for Service Engineers, 2012
Figure 12.6 shows the circuit diagram of a simple JFET amplifier. It is the equivalent circuit to that shown for the bipolar common emitter amplifier and operates in a similar manner. The correct bias to the gate must be applied and this is with the gate less positive than the source. R1 produces this condition. R3 is the load resistor and determines the amplitude of the output signal for a given input signal and current. When the signal at the gate goes positive the depletion layer in the N channel is reduced so with a larger conducting channel more current flows resulting in a fall in voltage on the drain. When the signal at the gate goes negative the depletion layer increases so the conducting channel becomes narrower and less current flows. The voltage on the drain rises. Once again the signal on the drain is an inverted but larger signal than that at the gate. Just as in the common emitter amplifier the signal on the collector was a larger but inverted signal than that applied to the base. C1 and C2 are coupling capacitors. Their purpose is to allow the ac signal to pass but to block any dc voltage that may be present with the input signal which would change the dc bias conditions and possibly damage the FET. R2 is a gain control since reducing its value allows more current to flow, whilst increasing its value reduces the gain because less current flows. C3 prevents any ac signal being developed across R2 and reducing the gain.
Transistor Modeling and Simulation
Published in Abdullah Eroglu, Introduction to RF Power Amplifier Design and Simulation, 2018
Once the network analyzer had been calibrated by means of a two-port calibration using the SOLT method with the designed calibration standards, as shown in Figures 3.34 and 3.37, the biasing circuit depicted in Figure 3.38 is simulated with the nonlinear circuit simulator of Ansoft Designer and implemented to characterize the active device, BFR92, for various biasing conditions. Simulation of the biasing circuit is needed to determine the best DC biasing conditions. DC bias conditions can be determined by adjusting the voltage sources Vbase and Vcollector while maintaining constant current limiting resistors Rbase and Rcollector. A 425-nH inductor was placed in series with each current limiting resistor with their respective transistor pins in order to isolate these ports from the DC biases at microwave frequencies. The inductor selected (PN: CC21T36K2406S) is a conical inductor whose resonance frequency was greater than 1 GHz. In addition, a 0.033-μF capacitor was added in order to form a low-pass filter with the current limiting resistors. The sole purpose of this RC was to provide a clean DC supply at the base and collector of the transistor under test. Utilizing the test setup shown in Figure 3.39, the BFR92 transistor could be easily tested under various bias conditions with the help of simulation. The circuit shown in Figure 3.39 is constructed, and characterization of the device has been performed under bias, as shown in Figure 3.40. The complete network analyzer measurement test setup used for characterization is illustrated in Figure 3.41.
Polarization Reconfigurable Corner Truncated Square Microstrip Array Antenna
Published in IETE Journal of Research, 2021
Bharathi Anantha, Lakshminarayana Merugu, Somasekhar Rao P.V.D
A polarization reconfigurable corner truncated Square Microstrip Patch Antenna (SMSPA) is designed as an array element. The antenna element under consideration is detailed in [15] and it is repeated here only to recollect the basic configuration of the antenna element. Figure 1 shows configuration of the antenna element with detailed dimensions. It is designed on 1.6 mm thick RT/Duroid 5880 substrate with relative permittivity ϵr = 2.2. The ground plane dimensions are Lg × Wg = 40 mm × 40 mm. The feed arrangement consists of a quarter-wave transformer which improves the impedance match between the antenna and 50 Ω feed network. Figure 1(a) depicts the top view of the antenna. It shows four PIN diodes D1 to D4 located in the slots cut at the four corners of the square patch. Independent bias voltages control ON/OFF switching states of the PIN diodes. The bias circuit consists of five DC terminals V1, V2, V3,V4 and V5 which act as bias pads. DC bias voltage is applied to the terminals V1 to V4 for biasing the PIN diodes. These bias pads are connected to parasitic triangular conductors through inductors of 47 nH to isolate DC and RF. A λ/4 bias line connecting the terminal V5 to corner truncated patch provides a high impedance to RF signals. However, it provides DC ground by shorting the terminal V5 to ground through printed through hole (PTH).
Flat frequency comb generation employing cascaded single-drive Mach–Zehnder modulators with a simple analogue driving signal
Published in Journal of Modern Optics, 2021
Mahmoud Muhanad Fadhel, Haroon Rashid, Abdulwahhab Essa Hamzah, Mohd Saiful Dzulkefly Zan, Norazreen Abd Aziz, Norhana Arsad
For a single-drive MZM, the voltage is applied only on one arm, unlike dual-drive MZM, and the optical spectrum output is given by Equation (1) [4] where is the modulation index, is the bias voltage, and is the voltage of the modulation signal. Compared to a phase modulator (PM), the bias voltage adds a degree of freedom. DC bias voltage is used to set the MZM operating point, which can be maximum, quadrature, or minimum point, as shown in Figure 1(b). These degrees of freedom (amplitude/frequency of RF signal and DC bias voltage) can shape the OFC lines by producing a flat spectrum. This feature can find applications in spectroscopy and in time domain applications where short pulses are required; power variation in comb line-to-line results in low pulse quality [4, 11]. Driving the electro-optic modulator, with optimum values of RF and DC bias voltages, is the key to generate frequency comb with a flat spectrum. These values can be found experimentally or by a complex mathematical modelling using the Bessel function [12]. Earlier reports used SD-MZM to generate flat frequency comb, but along with multiple RF modulation signals [13] or cascaded with dual-parallel MZM [14], which require three DC bias voltages to avoid bias drift issues.
Photonic generation of triangular-shaped waveform signal with adjustable symmetrical coefficient
Published in Journal of Modern Optics, 2019
Jing Li, Tigang Ning, Li Pei, Jingjing Zheng
It has to be mentioned that the influence of the dc bias drift on the stability of the generated triangular waveform should be considered. In theory, different dc bias voltage means different harmonic coefficient (2m−1 and 2m in Equations (4) and (5)). Since the triangular waveform construction is totally based on harmonic amplitude manipulation, the dc bias drift seems to be the biggest problem. Fortunately, this problem can be avoided. In our work, three variables (β, ϕ, and Ωτ) should meet the relationship of Equations (15-1) and (15-2). Three variables and two equations means at least one variable can be set randomly. In our work, the modulation index is fixed as a constant value (β = 1.5). If we want to focus on the bias drift problem. We may set ϕ as a constant value and adjust the other two variables. With the help of the bias voltage control circuit, the impact of the bias drift problem can be minimized in our work.