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Structured Digital Design
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
As shown in Figure 7.7(a), a complex operation involves three sequential operations. Assume input A takes one of the three values A1, A2, or A3. The operation chain can be triplicated, each copy of which has the A input fixed to one of its values. Through constant propagation, OP1 can be optimized and sped up. The results of the three copies are selected through a multiplexer controlled by A. The carry select adder is an application of this kind of generalized select transformation. Another kind is the generalized bypass transformation [3], the application of which is the carry skip adder. Figure 7.7(c) shows an example. Inputs C and D are used to produce the “bypass” or “skip” signal, indicating whether Z can be solely represented by the output of OP1.
An Efficient Technique for Image Compression and Quality Retrieval in Diagnosis of Brain Tumour Hyper Spectral Image
Published in K. Gayathri Devi, Kishore Balasubramanian, Le Anh Ngoc, Machine Learning and Deep Learning Techniques for Medical Science, 2022
V.V. Teresa, J. Dhanasekar, V. Gurunathan, T. Sathiyapriya
The design starts with the aim of reducing the area of the CSLA adder. Thus to reduce the area, we take a big action to eliminate the multiplexer in the CSLA which selects the sum and carry outputs of the adder. Actually, we cannot just modify the design simply; specifically the elimination of the mux is to be studied in detail. Because it can change the whole operation of the adder and in turn affect the performance of the adder. The CSLA without mux can be designed by giving the carry input directly to the AOI block. The AOI of the CSLA for the elimination of mux is shown in Figure 2.5. The AOI that includes another set of AND, OR and inverter gates to receive carry the input from the previous block. The AOI obtains the carry and computes it with the block's sum and carry. As in previous work, the CSLA is separated into groups here. The full 16-bit CSLA in groups and its interconnections are shown in Figure 2.6. Except for the least-significant, Each sector of a carry-select adder conducts two adds in parallel, one with a carry-in of zero and the other with a carry-in of on. Two ripple carry adders and a multiplexer make comprise a four-bit carry select adder. The carry-select adder is simple but fast, with an O(n) gate-level depth. When using a carry select adder to add two n bit values, two adders (two ripple carry adders) are utilized, one with the carry supposed to be zero and the other with the carry assumed to be one. Where, S=A+B+Cin
Sub-System Design
Published in M. Michael Vai, Vlsi Design, 2017
The addition time of a ripple-carry adder can be improved with a modified structure called the carry select adder. It retains the layout regularity of a ripple-carry adder. The principle of a carry select adder is to use one ripple-carry adder to execute an addition assuming that the carry-in is 1. Another ripple-carry adder is used to execute the same addition assuming that the carry-in is 0. The real carry-in computed in a previous stage is used to select one of the two sums with a multiplexer. Fig. 7.4 shows an example of an 8-bit carry select adder with a 4-4 staging. The 4-4 staging specifies that two stages are to be used, each of which performs the addition of 4 bits.
High Performance Error Tolerant Adders for Image Processing Applications
Published in IETE Journal of Research, 2021
To avoid large error, CFA based RCA is implemented for normal addition rule in the accurate part. The special function rule is implemented in the inaccurate part to check every bit position from the central position to LSB. When both input values are “1” in the inaccurate part, all sum bits of that appropriate sum to the LSB position is set to “1”. If values are “0” or different, normal XOR function is performed and operation proceeds to the next LSB position [14]. CLA and RCA logic are used in the accurate part for improving the area and speed in the ETA-II design. Since there is no carry signal generated, the propagation path will not exist. Energy efficient Low power Area efficient Error Tolerant Adder (ELAETA-I or ELAETA-II) has error sensitive circuit in the most significant bit position of the inaccurate part, which computes the carry and the appropriate addition of carry to the least significant bit position of the accurate part. It increases the accuracy when normal OR operation is performed instead of XOR operation on the inaccurate part of area efficiency over the existing ETA-I or ETA-II, respectively [14] as shown in Figure 6 (b). When the input operands values are “255” or “127”, the 16-bit ETA or ELAETA family exhibits 50% worst case error and the overall computational accuracy is lesser than 50% for low-value inaccurate part operands ranging from 0 to 255. A carry-select adder has 40% to 90% faster speed than a ripple carry adder by performing additions in parallel and reducing the maximum carry path delay.
The recursive multiplexer based multipliers
Published in International Journal of Electronics Letters, 2020
As shown in Figure 4, a carry-select adder performs an n bit addition by three half-size adders and one 2 to 1 multiplexer. Higher bits are processed by two adders in parallel. One assumes the carry-in C is 0 whereas the other assumes it is 1. While the two duplicated adders process the higher bits, the third adder processes the lower bits and determines the lower product bits as well as the carry-out bit C. Using bit C as the select line of the multiplexer, the correct result is chosen. Assuming that the Mux delay is trivial, the CSL improves the propagation delay by approximately 50%, at the expense of higher hardware cost.
Design of approximate reverse carry select adder using RCPA
Published in International Journal of Electronics Letters, 2023
Rajasekhar Turaka, Koteswara Rao Bonagiri, Talla Srinivasa Rao, Gundugonti Kishore Kumar, Sudharsan Jayabalan, V. Bharath Sreenivasulu, Asisa Kumar Panigrahy, M. Durga Prakash
Figure 5 shows the carry select adder with 28 T Full adders. In this structure, it consists of both ripple carry adders and multiplexers. It performs n-bit addition with carry input as 0 and with 1 simultaneously. Final sums and carry outputs are decides by the multiplexers. The carry input is applied to selection line of multiplexer which decides the sum and carry outputs whether 0ʹs outputs or 1ʹs outputs generated by ripple carry adders. Carry select adder is better parameter like delay, power, and compared to other conventional adders.